Abstract: A programmable processing device has a built-in a program memory (14) for storage of data including program instructions for controlling a functional unit (20) of the device. The device also includes signature generating means (18) for combining data read from all locations of the memory (14) during a memory test sequence, to generate a signature word which can be used to verify correct programming and operation of the memory. The device includes means for supplying the generated signature word to an instruction decoding means (20) at the end of the memory test sequence for execution as a normal program instruction. The signature word thus directly determines subsequent operation of the device, enabling the verification result to be communicated externally without the need for a dedicated data path for communicating the signature value itself outside the device. Any desired signature word/instruction can be achieved by including a seed word in the stored data.

Abstract: A data transmission system which provides differential transmission of a multi-level interface corresponding to a binary interface formed by a plurality of binary input signals. The binary interface is encoded by an encoder into a corresponding multi-level differential interface formed by a plurality of multi-level signals, such correspondence being in accordance with a pre-selected code conversion table, and the respective multi-level signals are transmitted over respective transmission channels. Upon reception at a decoder, the signs of the differences between respective pairs of the multi-level signals are detected, and in accordance with such signs binary values are assigned to respective binary output signals of the decoder in accordance with the inverse of the code conversion table employed for encoding. Differential transmission achieves immunity from common mode noise, and multi-level encoding requires fewer channels than would be necessary for binary differential transmission.

Abstract: A programmable logic circuit for deriving any selected combinational logic function of a plurality of input logic signals, a particular logic function being established by programming signals supplied to the logic circuit. The circuit is a branching tree structure of successive gating levels, each gating level receiving a respective input logic signal and including one or more pairs of logic switches, each such gating switch being a bipolar transistor or a CMOS pair. Each pair of gating switches in a given gating level is coupled to one of the gating switches in the preceding gating level. A programming level following the highest gating level includes respective pairs of logic switches for the respective programming signals, each such pair driving one of the gating switches in the highest gating level. The logic circuit can serve as a prototype which can be programmed and reprogrammed during debugging of a programmable logic device (PLD) in which it is included.

Abstract: An electronic circuit contains a main stage (10 and 12) that produces a digital code consisting of a plurality of bits (B.sub.1 -B.sub.M-1) that make binary transitions as a function of an input parameter (V.sub.I). A synchronization stage (14 and 16) synchronizes transitions of bits (B.sub.0 -B.sub.K-1) in one part of the code with corresponding transitions of bits (B.sub.K -B.sub.M-1) in another part. When the input parameter is in transition regions where bits in the first-mentioned part of the code could go to wrong values, the synchronization stage suitably replaces the values of bits in the first part with information based on bits in the other part.

Abstract: The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Abstract: An error correction circuit employs a digital averaging technique to overcome transition bit errors in a plurality of original binary bits ideally arranged as a thermometer or circular code. The circuit first generates a like plurality of intermediate signals respectively corresponding to the original bits. Each intermediate signal varies according to a weighted analog summation of a specified odd number of consecutive original bits centered about the corresponding bit. The circuit then compares the intermediate signals with corresponding further signals to produce a corrected code.