Abstract: A DRAM chip with a data I/O-interface of an access width equal to a page size.

Abstract: To estimate physical properties of a wired or wireless transmission channel it is proposed to sample a signal, received via the transmission channel, for example a system response of the corresponding transmission system, in order, on the basis of the sampled values thus obtained, to ascertain the moments of the order 0 . . . n of the received signal. Using these moments of the order 0 . . . n, n parameters of a transmission function of the transmission channel can be determined, wherein the parameters can be polynomial coefficients, zero points or coefficients of a residual notation of the transmission function. Using this transmission function the physical properties of the transmission channel, such as the attenuation and dispersion properties, can be determined exactly or at least approximately assessed.

Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

Abstract: Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal.

Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Abstract: A memory device comprising at least a plurality of memory cells and a memory control unit to read and write user data to said memory cells is provided. The memory device comprises further a monitoring unit for retrieving a plurality of data concerning the memory device and a comparing unit. The comparing unit receives an output signal of the monitoring unit and is configured to compare the plurality of retrieved data with a plurality of reference values.

Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

Abstract: A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.

Abstract: A circuit includes a data conversion circuit including a first input configured to receive a first serial data stream, a second input configured to receive a second serial data stream, and a third input configured to receive a third serial data stream. A first sampling circuit is coupled to the first, second, and third inputs and is configured to sample the first to third data streams based on a plurality of clock signals and to generate a corresponding plurality of first sampled signals. A second sampling circuit is configured to sample the plurality of first sampled signals based on a further clock signal. The further clock signal has a clock frequency different from a clock frequency underlying the first to third serial data streams.

Abstract: In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path.

Abstract: A device for the production of standard compliant signals, for example pulse-type signals in a telecommunication network, serves the production and adaptation and/or pre-distortion of signals with a certain signal form, which is defined dependent on a standard signal form specified in a standard. The device comprises signal generation means (10) for the production of the signals with a certain signal form and signal adjustment means (20) for the adaptation or pre-distortion of the signals. The signal generation means (10) according to the invention are digitally realized, by using a programmable shift register (14), which contains multipliers specified by the standard signal form for multiplication with a digital input signal (1). The signal adjustment means (20) comprise substantially scalable digital filter arrangements in the form of a serial connection of digital filters (22) with a downstream multiplexer (24).

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: A clock and data recovery unit for recovering a received serial data bit stream having: phase adjustment means for adjustment of a sampling time in the center of a unit interval of the received data bit stream, wherein the phase adjustment means comprises means for generating equidistant reference phase signals, a phase interpolation unit, an oversampling unit, a serial-to-parallel-conversion unit, a binary phase detection unit, and a loop filter; and data recognition means for recovery of the received data stream which includes a number of parallel data recognition FIR-Filters, wherein each data recognition FIR-Filter comprises a weighting unit, a summing unit, and a comparator unit.

Abstract: The invention relates to a transmitter for transmission of digital data via a transmission line (10), comprising a current-driving digital/analogue converter (1) which is arranged at the input of the transmitter; a current-operated form filter (2) for forming the current pulses which are supplied from the digital/analogue converter; a line driver (5) which carries out current/voltage conversion; and a circuit for offset compensation (6), which is arranged in a feedback path (11). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.

Abstract: Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.

Abstract: A method processes data in a memory arrangement. The method includes receiving and transmitting the data from the memory arrangement in the form of data packets according to a predefined protocol. The method includes distributing each received data packet to at least two separate data packet processing units. Each data packet processing unit is coupled to a portion of memory cells of the memory arrangement. The method includes processing, at each data packet processing unit, parts of the received data packets that relate to the portion of the memory cells the data packet processing unit is coupled to. The method includes generating a data packet to be transmitted including setting up, with each data packet processing unit, a part of the data packet to be transmitted.

Abstract: The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set si