Abstract: High level synthesis techniques are disclosed, particularly, techniques for synthesizing pipelines having distributed control. In some implementations, an algorithmic description for a device design is first identified. Subsequently, a data-flow representation of the algorithmic description is generated; the data-flow representation including a plurality of operations. The plurality of operations are then scheduled, following which, a plurality of pipeline stages are generated corresponding to ones of the plurality of operations. Control logic for the pipeline stages may then be generated, followed by the generation of a netlist representation of the electronic device design based in part upon the scheduling of operations and pipeline stages.

Abstract: A behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations for modifying the allocation of variables to interface resources.

Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.

Abstract: A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.

Abstract: Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset of variables in a separately accessible memory space, and accessing one of the stored subset of variables to recover a stored value of the one of the stored subset of variables for use by at least one of the plurality of loops during synthesis. According to another embodiment, a method comprises identifying at least a first loop and a second loop, determining whether a dependency exists between the first loop and the second loop, and merging the first loop and the second loop into a single merged loop, wherein the merging comprises mapping a plurality of memory accesses from the first loop to a sliding window.

Abstract: Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent loops, dependent loops or some combination thereof. Other embodiments for processing loops are disclosed, as well as integrated circuits and circuit design databases resulting from the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.

Abstract: A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circuit. The behavioral synthesis tool reads the source code description and generates a synthesis intermediate format stored in memory. The synthesis tool searches the in-memory synthesis intermediate format to find loops. The loops are then listed in a graphical user interface (GUI) in hierarchical fashion. The GUI also lists loop configuration information associated with the loops, such as loop frequency, loop unrolling and loop pipelining. The GUI allows the designer to modify the loop configuration information without having to update the source code description.