Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

Abstract: A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being “empty” and “full”, respectively.

Abstract: An input signal latching circuit for suppressing the effect of any ringing or other irregularities that occur within a specified time period after a transitional voltage level is reached, without significantly delaying the propagation of the input signal.

Abstract: A first in, first out (FIFO) memory system and method in which the full or empty condition of the FIFO memory is detected before the FIFO memory is actually full or empty, thereby allowing the generation of FULL or EMPTY control signals immediately after a last data value is written into or from the FIFO memory. An almost-empty condition, is detected by comparing the read address and write address values. When the read and write address values indicate that one data value remains in the FIFO memory and a read operation is about to be performed, an ALMOST_EMPTY control signal is applied to a data input terminal of a first register that is clocked by a read clock signal. The ALMOST_EMPTY control signal is latched by the first register at the next rising edge of a read clock signal, thereby causing the register to generate a high EMPTY control signal in the same read clock cycle during which the last data value is read from the FIFO memory.

Abstract: A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

Abstract: The invention provides a Field Programmable Gate Array (FPGA) that initiates its own reconfiguration by driving its own output terminal and its own connected PROGRAM input terminal, permitting reliable self-reconfiguration of the FPGA. The signal forwarded to the PROGRAM input terminal triggers a reconfiguration sequence that, in turn, causes the signal received from the output terminal to be ignored. Therefore, the method of the invention is reliably stable and does not undesirably repeat, oscillate, or fail. The FPGA may initiate its own reconfiguration upon detecting that a new configuration bitstream has been selected for downloading from an external device such as a PROM. The FPGA may detect the actuation of a binary or rotary switch. Alternatively, the FPGA may detect when a CMOS latch or register points to a new configuration address in the PROM. In one embodiment, an external memory device stores FPGA state information from one reconfiguration cycle to the next.

Abstract: A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

Abstract: An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

Abstract: A circuit separately measures one or both of the rising-edge and falling-edge signal propagation delays through a signal path of interest. The greater of these delays can then be used to establish a worst-case delay for the signal path. The worst-case delay can be used, in turn, to create accurate timing specifications for logic circuits that include similar or identical signal paths. To determine the delay through the signal path, the signal path is used with a second, typically identical, signal path to create alternating feedback paths of an oscillator. The oscillator is configured to output a test-clock signal having a period proportional to either the rising- or falling-edge delays through the two signal paths. The test-signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the signal path of interest.

Abstract: A radiation-tolerant logic circuit includes three similarly configured SRAM-based PLDs. These PLDs work in parallel to provide identical logic functions. To guard against data corruption that can result from radiation-induced upsets, the logic circuit includes a state-comparison circuit that periodically performs a bitwise comparison of the configuration and user data from each of the PLDs; if a bit from one PLD differs from the corresponding bit from the others, the state-comparison circuit sets a flag that indicates that the differing PLD is in error. The erroneous PLD is then reprogrammed using error-free state data. In one embodiment, the error-free state data is read from an error-free PLD.

Abstract: A closed loop clock delay adjustment system measures the drift between the delay introduced by clock buffers and by delays inserted at the device data input pins. The system uses a reference delay at the input of a measurement flip-flop. The reference delay is defined to be an approximate average of the delays at the data input pins. An external clock signal is coupled to the input of the reference delay. The output of the reference delay is coupled to the data input of the measurement flip-flop. The external clock signal is also coupled to the input of a variable clock delay buffer sub-circuit. The output of the variable clock delay buffer is coupled to the clock signal input of the measurement flip-flop. In operation, the measurement flip-flop compares the variable clock delay buffer output signal with the clock signal delayed by the reference delay. If the variable clock delay buffer output signal is delayed more than the reference delay output signal, the variable clock delay is decreased.

Abstract: An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output.

Abstract: A structure and method for determining whether a first in, first out (FIFO) memory is empty or full when the read address of the memory equals the write address of the memory. The read and write addresses are individually incremented, using a Grey code to avoid decoding glitches. The address space is circular and is divided at least three segments. Portions of the read and write addresses are encoded to indicate the segments in which the read and write addresses are located. These encoded address portions are decoded to determine the relative segment positions of the read and write addresses. If the read address is in the segment prior to the write address, a DIRECTION signal is set to a first state. If the write address is in the segment prior to the read address, the DIRECTION signal is set to a second state. When the read address equals the write address, the state of the DIRECTION signal is used to determine whether the memory is empty or full.

Abstract: A structure and method for determining whether a first in, first out (FIFO) memory is empty or full when the read address of the memory equals the write address of the memory. The read and write addresses are individually incremented, each in a predetermined circular sequence. The circular sequence is divided at least three segments. Portions of the read and write addresses are encoded to indicate the segments in which the read and write addresses are located. These encoded address portions are decoded to determine the relative segment positions of the read and write addresses. If the read address is in the segment prior to the write address, a DIRECTION signal is set to a first state. If the write address is in the segment prior to the read address, the DIRECTION signal is set to a second state. When the read address equals the write address, the state of the DIRECTION signal is used to determine whether the memory is empty or full. If the DIRECTION signal is in the first state, the memory is empty.

Abstract: An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output.

Abstract: The present invention provides a bus protocol interface circuit for the peripheral units that prevents a conflict in bus requests between the peripheral units and permits bipolar drivers to be used for fast operation. The interface circuit comprises a logic means coupled to the bus acknowledgment line input terminal and the bus acknowledgment line output terminal for generating a logic output signal responsive to the signals on the bus acknowledgement line input and output terminals, and latching means coupled between the bus request line and the bus request line terminal, and further connected to the output of the logic means and the bus acknowledgment line output terminal, for latching into a state consistent with a bus request signal from any one of the peripheral units and for unlatching from the consistent state upon receipt of a bus acknowledgment signal in response to the bus request signal.

Abstract: In a digital data communication receiver, an apparatus for estimating the time of zero-crossing between successive samples of a continuous frequency shift keyed (FSK) or like zero-crossing signal in a manner more accurate than is provided by the basic sampling clock. The apparatus includes means for sensing a change in sign relative to successive samples of the signal and means responsive to the sensed sign change to interpolate between the values of the respective samples for indicating more accurately the time of occurrence of the zero-crossing prior to the second sample, thereby demodulating the continuous signal.

Abstract: A programmable counter is described having three cascaded counters, the first one of which is a dual modulus prescaler. The second counter is a resettable binary counter which is fed information from a programmable read-only memory as to the numbers of times the prescaler divisions are to be repeated. The third counter is a binary counter which further divides the frequency and controls the repetition numbers delivered by the programmable read-only memory to the presettable binary counter.

Abstract: A phase-locked loop frequency synthesizer is described not having the uncontrolled modulation of its output normally associated with such a synthesizer due to a detection dead band inherent in the phase/frequency comparator which is a principal part thereof. The frequency synthesizer includes, as is conventional, a reference oscillator and an oscillator for generating the synthesizer output. The comparator is also included as is conventional to detect unwanted deviations of the phase and frequency of the synthesizer output so they can be corrected. In order to compensate for the inability of the comparator to detect small unwanted deviations, a pulse generator is added to the synthesizer to apply what is, in effect, an intentional periodic phase error signal greater than the dead band difference. This causes the phase of the desired output to be corrected in a controlled manner which will prevent undesired frequency modulation of its output.