Abstract: Enables an I/O channel program to use IDAWs (indirect data address words) to control data transfers from/to an I/O (input/output) device to/from either or both of ES (expanded storage) and/or system MS (main storage), in which data moved to/from ES does not move through MS. ES and MS are plural electronic storage media in a data processing system, and the I/O device is any I/O device selectable by the system. Intermixing of data transfers between ES and MS may be controlled by a single IDAW list accessed by a channel control word (CCW) in a channel program in a data transfer direction indicated in the CCW without any channel mode change.

Abstract: An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage.

Abstract: A system and method for dispatching logical central processing units (CPUs) among physical CPUs in a multiprocessor computer system having multiple logical partitions, wherein the cryptographic facilities may not be interchangeable. According to the present invention, the logical CPUs are dispatched among the physical CPUs according to either an affinity, floating, or disabled scheduling method. The affinity scheduling method is used when the crypto facilities are not interchangeable or when non-interchangeable crypto functions are performed. The floating scheduling method is used when the cryptographic facilities are interchangeable and interchangeable crypto functions are performed. The disabled scheduling method is used when the logical CPU is not authorized to issue cryptographic instructions.

Abstract: A data processing system operated with multiple levels of virtual machine guests under a host control program. The second level of guests are invoked, operated, and terminated without host intervention, as has been required in prior systems, to significantly increase the operating efficiency of the system. Address translation is done by providing machine capability to translate second level guest addresses to real memory addresses taking advantage of the first level guest being located at a simple offset within real memory. Special facilities for second level guests periodically test for timing interruptions for second level guests and update the second level guest timing facilities.

Abstract: A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB.

Abstract: A CPU interface recognizing a large very number of I/O interruption queues in a logically partitioned data processing system. Different partitions may contain different guest operating systems. The CPU interface controls how plural CPUs respond to I/O interruptions put on numerous hardware-controlled queues. A host hypervisor program dispatches the guest operating systems. The guests use the I/O interruptions in controlling the dispatching of their programs on the CPUs in a system. The invention allows the number of guest partitions in the system to exceed the number of I/O interruption subclasses (ISCs) architected in the system, and enables the dispatching controls of each guest operating system to be sensitive to different priorities for plural programs operating under a respective guest. The invention provides CPU controls that support alerting the host to enabled I/O interruptions, and provides CPU controlled pass-through for enabling direct guest handling of the guests I/O interruptions.

Abstract: The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions.

Abstract: The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity.

Abstract: The disclosure describes a separate trace table for each CPU in an MP to avoid inter-CPU interference in making trace table entries for explicit and implicit tracing instructions enabled by flag bits in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing instruction. Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand of the trace instruction contains a disablement field and optionally may contain an enablement-controlling class field to improve the integrity of traceable programs. A time stamp and range of general register contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.

Abstract: The embodiment obtains rapid switching between system control programs (SCPs) by switching an address in a prefix register in a CPU of a MP or UP data processing system from a guest SCP's PSA (program save area) to a host SCP's PSA by fetching the host prefix value from a predetermined control block in main storage. The prefix register loading changes the control of the CPU from a preferred guest SCP to a host SCP. This SCP switching is done by hardware and/or microcode means in the CPU. It further detects preset states in the CPU that enable a rapid determination of which SCP is to handle a sensed event, permitting the guest SCP to immediately handle events predetermined to belong to the guest. This manner of CPU control obtains for a preferred guest SCP (such as MVS/370) operating under a host SCP (such as VM/370) nearly the efficiency of standalone execution on the CPU by the preferred guest SCP.

Abstract: Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.