Patents by Inventor Peter Howard Spalding
Peter Howard Spalding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6963124Abstract: A panel assembly of packaged integrated circuit devices including a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.Type: GrantFiled: September 17, 2004Date of Patent: November 8, 2005Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6933174Abstract: A leadless leadframe semiconductor package having a plurality of contacts, which have contact surfaces on the bottom surface of the package. At least some of the contacts have integrally formed stems that extend outward to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates at least a portion of the die, the stems and the contacts. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts. The contacts also have integrally formed stems that extend towards and connect to one of the tie bars. The stems have widths and heights that are less than the widths and heights of their corresponding contacts.Type: GrantFiled: September 30, 2004Date of Patent: August 23, 2005Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6818970Abstract: A leadless leadframe semiconductor package includes a plurality of contacts, at least some of which have integrally formed stems that extend to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates the stems and the contacts to leave contact surfaces of the contacts exposed on the bottom surface of the package. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, which has a plurality of tie bars and a plurality of contacts. The contacts have integrally formed stems that extend towards and connect to one of the tie bars. The stems have widths and heights that are less than the widths and heights of their corresponding contacts.Type: GrantFiled: August 11, 2003Date of Patent: November 16, 2004Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6808961Abstract: A panel assembly of packaged integrated circuit devices comprising a conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The locking passageways extend from a topside of the panel toward a bottom side of the panel. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.Type: GrantFiled: April 14, 2003Date of Patent: October 26, 2004Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6677667Abstract: A leadless leadframe semiconductor package comprising a plurality of contacts, which have contact surfaces on the bottom surface of the package. At least some of the contacts have integrally formed stems that extend outward to the peripheral surface of the package. These stems have heights and widths less than the heights and widths of their corresponding contacts. A molded cap encapsulates at least a portion of the die, the stems and the contacts. The molded cap leaves the contact surfaces of the contacts exposed on the bottom surface of the package, leaves a peripheral surface of the stems exposed on the peripheral surface of the package, and covers a bottom surface of each of the stems. Another aspect of the invention pertains to a leadless leadframe panel assembly having a conductive substrate panel that has at least one array of device areas, each array of device areas having a plurality of tie bars and a plurality of contacts.Type: GrantFiled: November 28, 2000Date of Patent: January 13, 2004Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6674156Abstract: A leadless leadframe panel comprising a partially etched top surface of a substrate panel that forms recessed regions that define a portion of a first and a second set of tie bars and a portion of a first and second set of contact pads. A bottom surface of the panel forms lower recessed regions that define the remaining portion of the first and second set of tie bars and the remaining portion of the first and second set of contact pads. The resulting contact pads are connected to a respective one of the tie bars.Type: GrantFiled: February 9, 2001Date of Patent: January 6, 2004Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Peter Howard Spalding
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Patent number: 6617197Abstract: A packaging arrangement is described that utilizes a conductive panel (such as a leadless leadframe) as its base. The conductive panel has a matrix of device areas that each include a plurality of rows of contacts that are located outside of a die area. Tie bars provide support for the various contacts. Some of the tie bars are arranged to extend between adjacent contacts in the same row and some of the tie bars are arranged to extend diagonally between associated contacts in adjacent rows that are not adjacent one another. During packaging, the tie bars can be severed by cutting along lines (e.g. saw streets) that run adjacent the rows after a molding operation. The described panels are particularly useful in packages having three or more rows of contacts.Type: GrantFiled: November 15, 2001Date of Patent: September 9, 2003Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Peter Howard Spalding
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Patent number: 6576989Abstract: A panel assembly of packaged integrated circuit devices including conductive substrate panel having an array of device areas and a plurality of locking passageways. The locking passageways are positioned about an inactive buffer area which surrounds the periphery of the array of device areas. The locking passageways extend from a topside of the panel toward a bottom side of the panel. The panel assembly also includes a molded cap that is molded over the topside of the panel to encapsulate the array of device areas and the inactive buffer area. The molded cap includes conforming locking stem portions that extend into each of the locking passageways in a manner locking the molded cap to the substrate panel such that during singulation of the device areas, the molded cap will not separate from the substrate panel at the inactive buffer area. In another aspect of the invention, a method for producing the panel assembly having the locking passageways is described.Type: GrantFiled: November 28, 2000Date of Patent: June 10, 2003Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6551048Abstract: An off-loading system comprising an array of suction tubes which are each able to pick up an associated semiconductor device from the matrix of devices and a pump which pulls air through the suction tubes to create a sufficiently low pressure within the suction tubes to allow each suction tube to pick up an associated device. In another embodiment of the invention, the off-loading system also includes a pin board which supports an array of pins configured to raise a selected array of the semiconductor devices to assist in picking up the selected array of devices from the matrix of devices. Another embodiment of the invention includes a rack that includes multiple elongated rails which form multiple channels through which the semiconductor devices travel so that they may properly enter a subsequent phase of the manufacturing process.Type: GrantFiled: July 12, 2000Date of Patent: April 22, 2003Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Peter Howard Spalding
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Patent number: 6483180Abstract: A semiconductor device exhibiting a lower incidence of burrs forming on its contacts during the singulation process. The semiconductor device includes a die which is electrically connected to a set of contacts wherein each contact has a contact surface and a non-contact surface. Each contact surface of the contacts contains a recessed region filled with a first deposit of molding material. The die and the non-contact surfaces of the contacts are encapsulated with a second deposit of molding material. The semiconductor device is singulated from a molded lead frame by guiding a saw blade through recessed regions formed on the contact surface of the contacts. The molding material in the recessed regions creates a “buffer zone” which separates the path of the saw blade from the contact surface of the contacts.Type: GrantFiled: December 23, 1999Date of Patent: November 19, 2002Assignee: National Semiconductor CorporationInventors: Jaime A. Bayan, Peter Howard Spalding
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Patent number: 6452255Abstract: A variety of leadless packaging arrangements and methods of packaging integrated circuits in leadless packages that are arranged to have relatively low inductance are disclosed. In one aspect, a leadless semiconductor package is described having an exposed die pad and a plurality of exposed contacts that are formed from a common substrate material. The die attach pad, however, is thinned relative to at least a portion of the contacts. A die is mounted on the thinned die attach pad and wire bonded to the contacts. Since the die attach pad is lower than the contact surface being wire bonded to, the length of the bonding wires can be relatively reduced, thereby reducing inductance of the device. A plastic cap is molded over the die and the contacts thereby encapsulating the bonding wires while leaving the bottom surface of the contacts exposed. In some embodiments, the die is arranged to overhangs beyond the die attach pad towards the contacts.Type: GrantFiled: March 20, 2000Date of Patent: September 17, 2002Assignee: National Semiconductor, Corp.Inventors: Jaime Bayan, Peter Howard Spalding, Harry Cheng Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong
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Patent number: 6448107Abstract: Leadframe based packages, such as leadless leadframe packages are described that include an orientation indicator that is integrally formed with the leadframe. In one aspect, the leadframe includes a die attach pad, a plurality of contact fingers, a tie bar extending from the die attach pad, and an indicator stem extending from the tie bar. An integrated circuit die is mounted on the die attach pad and electrically coupled bond to associated contact fingers. A protective cap encapsulates the connectors and covers at least a portion of the die and contact fingers while leaving at least a portion of a bottom surface area of the contact fingers exposed to form external electrical contacts for the package. The protective cap leaves an identifying end of the indicator stem exposed through the surface of the protective cap to facilitate identification of a particular contact or region of the package. The described leadless leadframes may be produced in panel form which facilitates panel based packaging.Type: GrantFiled: November 28, 2000Date of Patent: September 10, 2002Assignee: National Semiconductor CorporationInventors: Harry Kam Cheng Hong, Hu Ah Lek, Santhiran Nadarajah, Sharon Ko Mei Wan, Chan Peng Yeen, Jaime Bayan, Peter Howard Spalding
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Patent number: 6399415Abstract: A variety of techniques for electrically debussing conductive substrate panels used in the formation of a matrix of leadless integrated circuit packages are described. Generally, after a matrix of leadless packages have been fabricated in panel form on a conductive substrate panel, tie bars that are used to support contacts and potentially other structures on the conductive substrate are removed after plastic caps have been molded over the matrix, but before separating the packaged devices. This serves to electrically isolate the contacts from one another while leaving sufficient portions of the molded substrate structure in tact to facilitate handling the structure in panel form. With the described arrangement, the packaged devices may be tested in panel form. After testing and any other desired panel based operations, the packaged devices may be separated using conventional techniques. The removal of the tie bars can be accomplished by any suitable technique including, for example, sawing or etching.Type: GrantFiled: March 20, 2000Date of Patent: June 4, 2002Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Peter Howard Spalding, Harry Cheng Hong Kam, Ah Lek Hu, Sharon Mei Wan Ko, Santhiran Nadarajah, Aik Seng Kang, Yin Yen Bong
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Patent number: 6372539Abstract: Improved methods of packaging integrated circuits in leadless packages are disclosed. A conductive substrate sheet is initially patterned to form troughs that define a multiplicity of device areas. Each device area includes a plurality of contact landings (and preferably a die attach pad) that are formed in substrate sheet by patterning. The patterning can be done using a variety of conventional techniques including etching. A multiplicity of dice are then attached to the substrate sheet and bond pads on the dice are electrically connected to associated contact landings using conventional techniques such as wire bonding. One or more caps are then molded over the device areas to encapsulate the dice and bonding wires and to fill the troughs. After the caps have been formed, excess portions of the substrate sheet (e.g. portions below the troughs) are removed to electrically isolate the contact landings thereby forming electrically isolated independent contacts in a molded package.Type: GrantFiled: March 20, 2000Date of Patent: April 16, 2002Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Peter Howard Spalding
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Patent number: 6348726Abstract: A packaging arrangement is described that utilizes a conductive panel (such as a leadless leadframe) as its base. The conductive panel has a matrix of device areas that each include a plurality of rows of contacts that are located outside of a die area. Tie bars provide support for the various contacts. Some of the tie bars are arranged to extend between adjacent contacts in the same row and some of the tie bars are arranged to extend diagonally between associated contacts in adjacent rows that are not adjacent one another. During packaging, the tie bars can be severed by cutting along lines (e.g. saw streets) that run adjacent the rows after a molding operation. The described panels are particularly useful in packages having three or more rows of contacts.Type: GrantFiled: January 18, 2001Date of Patent: February 19, 2002Assignee: National Semiconductor CorporationInventors: Jaime Bayan, Peter Howard Spalding
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Patent number: 5789806Abstract: A leadframe including bendable support arms for downsetting a die attach pad and method are disclosed herein. The leadframe includes at least one frame member and the die attach pad. At least two distinct, readily bendable support arms are connected with and extend between the die attach pad and the frame member. The support arms are configured to be bent in a predetermined way in the method of the invention such that when they are bent they provide previously unattainable amounts of die attach pad downset within the overall configuration of the leadframe.Type: GrantFiled: March 18, 1997Date of Patent: August 4, 1998Assignee: National Semiconductor CorporationInventors: Charlie Kho Chua, Ka-Heng The, Peter Howard Spalding