Abstract: Aspects relate to providing a status bit to a base station, where the status bit indicates whether all of multiple downlink transmissions have been successfully decoded. In an aspect, a user equipment (UE) receives a plurality of downlink transmissions from a base station, and generates a plurality of acknowledgement data respectively for the plurality of downlink transmissions, each of the plurality of acknowledgement data indicating whether a respective downlink transmission of the plurality of downlink transmissions has been successfully decoded. The UE further transmits, to the base station, at least one status bit based on the plurality of acknowledgement data, the at least one status bit indicating whether all of the plurality of downlink transmissions have been successfully decoded.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus for wireless communication at a wireless node comprises one or more memories, and one or more processors, coupled to the memory. The one or more processors can be configured to transmit or receive tri-state feedback indicating a result of decoding one or more communications. The tri-state feedback can be associated with three potential states. The three potential states can indicate whether (i) decoding of a control channel was unsuccessful, (ii) decoding of the control channel was successful and decoding of a data channel was unsuccessful, or (iii) decoding of the control channel and the data channel was successful.

Abstract: Aspects of the present disclosure provide techniques for triggering generation and transmission of a channel state information (CSI) report by the user equipment (UE) on physical uplink shared channel (PUSCH) in response to issuance of at least one downlink grant by the base station.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a configuration of a set of resources for sidelink coordination information requests. The UE may transmit a sidelink coordination information request message in at least one resource selected from the set of resources for sidelink coordination information requests. Numerous other aspects are provided.

Abstract: A twin beam base station antenna includes a first array that has a plurality of columns of first frequency band radiating elements, the first array configured to form a first antenna beam that provides coverage throughout a first sub-sector of a three-sector base station. The radiating elements in a first of the columns in the first array have a first azimuth boresight pointing direction and the radiating elements in a second of the columns in the first array have a second azimuth boresight pointing direction that is offset from the first azimuth boresight pointing direction by at least 10°. The radiating elements in the second of the columns in the first array are electrically steered.

Abstract: Systems and methods for a programming language-agnostic data modeling platform that is both less resource intensive and scalable. Additionally, the programming language-agnostic data modeling platform allows for advanced analytics to be run on descriptions of the known logical data models, to generate data offerings describing underlying data, and to easily format data for compatibility with artificial intelligence systems. The systems and methods use a supplemental data structure that comprises logical data modeling metadata, in which the logical data modeling metadata describes the logical data model in a common, standardized language. For example, the logical data modeling metadata may comprise a transformer lineage of the logical data model.

Abstract: A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

Abstract: An implantable device and method of manufacture include a substantially hermetic polychlorotrifluoroethylene (PCTFE) enclosure with closely-spaced wires extending out of the enclosure. The implantable device includes a PCTFE first portion of an enclosure and a PCTFE second portion of the enclosure. The first and second portions are configured to mate with each other to form the enclosure. A plurality of insulated wires extend between the first and second portions of the enclosure. Each of the insulated wires are parallel to each other and separated by less than 150 micrometers (?m) from a neighboring wire. A thermal weld seam of PCTFE is disposed between the first portion of the enclosure and the second portion of the enclosure and conformally adheres around insulation of each wire such that the enclosure is sealed.

Abstract: A capacitance device includes: a semiconductor substrate; a capacitor disposed on the semiconductor substrate and including first and second positive terminals and first and second negative terminals; a passivation layer formed over the capacitor, the first and second positive terminals and the first and second negative terminals, the passivation layer defining first and second openings over the first and second positive terminals, respectively, a third opening over the first negative terminal and a fourth opening over the second negative terminal; a first metallic bump disposed on the passivation layer and including first extending portions that extend through each of the first and second openings, electrically coupling the first and second positive terminals; and a second metallic bump disposed on the passivation layer and including second extending portions that extend through each of the third and fourth openings, electrically coupling the first and second negative terminals.

Abstract: A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

Abstract: Embodiments of the present disclosure provide a method and device for data center management. For example, there is provided a method, comprising: obtaining information of hardware used in a data center, the information of the hardware including identification information describing an identifiable attribute of the hardware; identifying the hardware by matching the identification information with a resource profile, the resource profile recording identifiable attributes of a plurality of types of hardware; and updating a record associated with the hardware in a database of the data center using the obtained information. Corresponding device and computer program product are also provided.

Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Abstract: A configurable capacitance device includes a semiconductor substrate including a plurality of integrally formed capacitors; and a separate interconnect structure coupled to the semiconductor substrate, wherein the separate interconnect structure is configurable to electrically couple two or more of the plurality of integrally formed capacitors together in a parallel configuration.

Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

Abstract: Embodiments of the present disclosure provide a method and device for data center management. For example, there is provided a method, comprising: obtaining information of hardware used in a data center, the information of the hardware including identification information describing an identifiable attribute of the hardware; identifying the hardware by matching the identification information with a resource profile, the resource profile recording identifiable attributes of a plurality of types of hardware; and updating a record associated with the hardware in a database of the data center using the obtained information. Corresponding device and computer program product are also provided.

Abstract: A universal serial bus (USB) memory is disclosed. The USB memory includes a housing having a plurality of orientated indentations and a plurality of concave props, wherein the plurality of orientated indentation facilitates the USB memory to be connected while the USB memory is inserted into a female USB socket; a print circuit board assembly (PCBA) disposed in the housing, wherein the PCBA is fixed by means of pressing of the plurality of concave props; and a LED module having a LED indicator disposed in the housing and a LED module controller disposed on the PCBA, wherein a space is formed between the housing and the PCBA for disposing the LED module.

Abstract: A universal serial bus (USB) memory is disclosed. The USB memory includes a housing having a plurality of orientated indentations and a plurality of concave props, wherein the plurality of orientated indentation facilitates the USB memory to be connected while the USB memory is inserted into a female USB socket; a print circuit board assembly (PCBA) disposed in the housing, wherein the PCBA is fixed by means of pressing of the plurality of concave props; and a LED module having a LED indicator disposed in the housing and a LED module controller disposed on the PCBA, wherein a space is formed between the housing and the PCBA for disposing the LED module.