Patents by Inventor Peter Igorevich Vasiliev

Peter Igorevich Vasiliev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8448045
    Abstract: Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: May 21, 2013
    Assignee: Seagate Technology LLC
    Inventors: Prafulla Bollampalli Reddy, Peter Igorevich Vasiliev, Hui Su, Timothy Richard Feldman, Mary Elizabeth Dunn, James Joseph Touchton, Bernardo Rub
  • Publication number: 20120304037
    Abstract: Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Prafulla Bollampalli Reddy, Mary Elizabeth Dunn, James Joseph Touchton, Bernardo Rub, Peter Igorevich Vasiliev, Hui Su, Timothy Richard Feldman
  • Patent number: 8086941
    Abstract: The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 27, 2011
    Assignee: Seagate Technology LLC
    Inventors: Clifton James Williamson, Peter Igorevich Vasiliev
  • Patent number: 7788560
    Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: August 31, 2010
    Assignee: Seagate Technology LLC
    Inventors: Cenk Argon, Richard Martin Born, Gregory Lee Silvus, Thomas Victor Souvignier, Peter Igorevich Vasiliev
  • Publication number: 20080215956
    Abstract: The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.
    Type: Application
    Filed: February 14, 2008
    Publication date: September 4, 2008
    Inventors: Clifton James Williamson, Peter Igorevich Vasiliev
  • Patent number: 7421642
    Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: September 2, 2008
    Assignee: Seagate Technology LLC
    Inventors: Clifton James Williamson, Peter Igorevich Vasiliev
  • Patent number: 7395461
    Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: July 1, 2008
    Assignee: Seagate Technology LLC
    Inventors: Cenk Argon, Richard Martin Born, Gregory Lee Silvus, Thomas Victor Souvignier, Peter Igorevich Vasiliev
  • Patent number: 7360147
    Abstract: A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 15, 2008
    Assignee: Seagate Technology LLC
    Inventor: Peter Igorevich Vasiliev
  • Publication number: 20040010742
    Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 15, 2004
    Applicant: Seagate Technology LLC,
    Inventors: Clifton James Williamson, Peter Igorevich Vasiliev
  • Publication number: 20030192005
    Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.
    Type: Application
    Filed: March 17, 2003
    Publication date: October 9, 2003
    Applicant: Seagate Technology LLC
    Inventors: Clifton James Williamson, Peter Igorevich Vasiliev