Patents by Inventor Peter Igorevich Vasiliev
Peter Igorevich Vasiliev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8448045Abstract: Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.Type: GrantFiled: May 26, 2011Date of Patent: May 21, 2013Assignee: Seagate Technology LLCInventors: Prafulla Bollampalli Reddy, Peter Igorevich Vasiliev, Hui Su, Timothy Richard Feldman, Mary Elizabeth Dunn, James Joseph Touchton, Bernardo Rub
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Publication number: 20120304037Abstract: Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.Type: ApplicationFiled: May 26, 2011Publication date: November 29, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Prafulla Bollampalli Reddy, Mary Elizabeth Dunn, James Joseph Touchton, Bernardo Rub, Peter Igorevich Vasiliev, Hui Su, Timothy Richard Feldman
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Patent number: 8086941Abstract: The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.Type: GrantFiled: February 14, 2008Date of Patent: December 27, 2011Assignee: Seagate Technology LLCInventors: Clifton James Williamson, Peter Igorevich Vasiliev
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Patent number: 7788560Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.Type: GrantFiled: March 20, 2008Date of Patent: August 31, 2010Assignee: Seagate Technology LLCInventors: Cenk Argon, Richard Martin Born, Gregory Lee Silvus, Thomas Victor Souvignier, Peter Igorevich Vasiliev
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Publication number: 20080215956Abstract: The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.Type: ApplicationFiled: February 14, 2008Publication date: September 4, 2008Inventors: Clifton James Williamson, Peter Igorevich Vasiliev
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Patent number: 7421642Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.Type: GrantFiled: July 10, 2003Date of Patent: September 2, 2008Assignee: Seagate Technology LLCInventors: Clifton James Williamson, Peter Igorevich Vasiliev
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Patent number: 7395461Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.Type: GrantFiled: May 18, 2005Date of Patent: July 1, 2008Assignee: Seagate Technology LLCInventors: Cenk Argon, Richard Martin Born, Gregory Lee Silvus, Thomas Victor Souvignier, Peter Igorevich Vasiliev
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Patent number: 7360147Abstract: A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.Type: GrantFiled: May 18, 2005Date of Patent: April 15, 2008Assignee: Seagate Technology LLCInventor: Peter Igorevich Vasiliev
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Publication number: 20040010742Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.Type: ApplicationFiled: July 10, 2003Publication date: January 15, 2004Applicant: Seagate Technology LLC,Inventors: Clifton James Williamson, Peter Igorevich Vasiliev
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Publication number: 20030192005Abstract: The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.Type: ApplicationFiled: March 17, 2003Publication date: October 9, 2003Applicant: Seagate Technology LLCInventors: Clifton James Williamson, Peter Igorevich Vasiliev