Abstract: The invention relates to a telecommunication network having IP packet-supporting capabilities, which includes a load distribution processing function, either centralized or distributed, by means of which a load distribution function may be applied to sets of paths between network nodes or sets of links of network trunks. The load distribution processing function handles different load distribution functions. Each of the different load distribution functions is associated to a different network input unit involved in the load distribution for a set of paths between network nodes or a set of trunk links. The invention also relates to a method of load distribution in a telecommunication network as summarized above.

Abstract: A method for packet reordering in a network processor, including the steps of processing packets, dividing the processed packets into a plurality of tiers and reordering the tiers independently from each other and collecting eligible packets from the plurality of tiers in a collector for forwarding. The method further includes the step of during the processing, determining the nominal packet processing time of each packet. The processed packets are divided into the plurality of tiers depending on the nominal packet processing time.

Abstract: The present invention relates to a switching unit with a low-latency flow control. Queuing parameters of ingress queues, wherein the incoming traffic is backlogged, are measured to detect a short term traffic increase. An additional bandwidth is then negotiated to accommodate this unexpected additional amount of traffic, provided that the corresponding input and output termination modules still dispose of available bandwidth, and disregarding temporarily fairness. This additional bandwidth allows this unexpected additional amount of traffic to be drained from the ingress queue as soon as possible, without waiting for the next system bandwidth fair re-distribution, thereby improving the traffic latency through the switching unit.

Abstract: The present invention relates to a switching unit with a scalable and QoS aware flow control. The actual schedule rate of an egress queue, wherein the outgoing traffic belonging to a particular class of service is backlogged, is measured and compared to its expected schedule rate. If the egress queue is scheduled below expectation, then the bandwidth of every virtual ingress-to-egress pipe connecting an ingress queue, wherein the incoming traffic belonging to the same class of service is backlogged before transmission through the switch core fabric, to that egress queue is increased, thereby feeding that egress queue with more data units.

Abstract: A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

Abstract: System for obtaining an efficient and scaleable flow control in a large packet switched network including ingress termination boards (B1?) linked to egress termination boards (B4?) by means of virtual ingress to egress flow control links through a switch core. The flow control transmission link between a port of an ingress termination board and a port of an egress termination board comprises at least two virtual ingress to egress flow controlled traffic pipes (VIEP?a, VIEP?b), one pipe handling all the traffic between the two ports which is going towards communication channels for which no congestion is detected at the level of the egress termination board, the other pipe handling all the traffic going towards communication channels for which congestion is detected.

Abstract: A method for sharing internal excess bandwidth between output and input termination modules of a switching network including a switch core fabric (FC) via which a plurality of input termination modules (ITM1 to ITMn) communicate with a plurality of output termination modules (OTM1 to OTMm) through at least a point-to-point transmission channels considered as corresponding each to a virtual ingress-to-egress pipe (VIEP). Sharing of internal excess bandwidth is obtained by successive steps including a minimum bandwidth request calculation step, each request being transmitted to an output termination module for obtaining a minimum bandwidth grant in return. The minimum bandwidth request and grant related to an input termination module linked by an ingress-to-egress pipe to an output termination module are both calculated for a determined number K of relative administrative weights corresponding each to a different quality of service, with a different request and a corresponding grant for every weight.

Abstract: A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

Abstract: A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue.

Abstract: The present invention is related to a method for packet reordering in a network processor (2), comprising the steps of Processing packets, Dividing the processed packets into a plurality of tiers and reordering said tiers independently from each other and collect eligible packets from the plurality of tiers in a collector for forwarding. The method further comprises the step of during the processing, determining the nominal packet processing time of each packet. The processed packets are divided into said plurality of tiers depending on said nominal packet processing time.

Abstract: The method applies to a telecommunication network having IP packet-supporting capabilities when said network includes a load distribution processing function which is either centralized or distributed and by means of which a load distribution function is applied to sets of paths between network nodes and/or sets of links (Lk1, Lkp) of network trunks (12).

Abstract: Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

Abstract: System for obtaining an efficient and scaleable flow control in a large packet switched network including ingress termination boards (B1″) linked to egress termination boards (B4″) by means of virtual ingress to egress flow control links through a switch core.

Abstract: The method shares available bandwidth on a common link in a communication network among a plurality of data flows which are transmitted via the common link. The method is used by a processor and includes sharing reserved bandwidth included in the available bandwidth among the plurality of data flows, and sharing unreserved bandwidth among the plurality of data flows according to a respective unreserved data packet share which is associated to each one of the plurality of data flows. The unreserved bandwidth is included in the available bandwidth in excess of the reserved bandwidth. The sharing of the unreserved bandwidth includes associating to one of the plurality of data flows a respective adaptable administrative weight and determining the respective unreserved data packet share which is associated to the one data flow as a function of its respective adaptable administrative weight.

Abstract: Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

Abstract: A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory subsystem includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

Abstract: The present invention relates to a method for sharing internal excess bandwidth between output and input termination modules of a switching network including a switch core fabric (FC) by means of which a plurality of input termination modules (ITM1 to ITMn) communicate with a plurality of output termination modules (OTM1 to OTMm) through at least point-to-point transmission means considered as corresponding each to a virtual ingress-to-egress pipe (VIEP).