Patents by Inventor Peter J. Kazarian
Peter J. Kazarian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7839167Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: January 20, 2009Date of Patent: November 23, 2010Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Publication number: 20090289660Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: ApplicationFiled: January 20, 2009Publication date: November 26, 2009Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Patent number: 7492188Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: July 30, 2007Date of Patent: February 17, 2009Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Patent number: 6989689Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: May 24, 2004Date of Patent: January 24, 2006Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Patent number: 6894533Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: June 9, 2003Date of Patent: May 17, 2005Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Publication number: 20040251930Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: ApplicationFiled: May 24, 2004Publication date: December 16, 2004Applicant: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Publication number: 20030210073Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: ApplicationFiled: June 9, 2003Publication date: November 13, 2003Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Patent number: 6407576Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: GrantFiled: March 2, 2000Date of Patent: June 18, 2002Assignee: Altera CorporationInventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
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Patent number: 5838584Abstract: A technique is used to implement chains into a programmable logic device. In one embodiment, the method includes solving a bin packing problem (step 105), test-placing a chain in each logic element position (step 401), forming groups of unused logic element positions (step 405), determining whether future chains can be placed in these remaining unused logic element positions (step 410), comparing each placement against a previously stored placement, and storing the logic element position of the more efficient logic element positions have been checked (step 210). In the end, a substantially optimum placement for each chain is found.Type: GrantFiled: April 4, 1997Date of Patent: November 17, 1998Assignee: Altera CorporationInventor: Peter J. Kazarian
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Patent number: 5670895Abstract: Logic signal routability in programmable logic array integrated circuit devices is improved by selecting the possible interconnections between various resources on the device so that various constraints or goals are satisfied. Improving routability in this way tends to reduce instances in which desired interconnections are blocked by other connections that have already been made.Type: GrantFiled: October 19, 1995Date of Patent: September 23, 1997Assignee: Altera CorporationInventors: Peter J. Kazarian, Bruce B. Pedersen, Francis B. Heile, David Wolk Mendel