Abstract: An arbitration network for use in a data multiprocessing system that includes a functional unit, such as a memory module, that is shared by several requestor devices, such as data processors, wherein access is granted to the shared functional unit through a common data bus on a rotating priority basis and wherein the arbitration cycle of the functional unit for determining priorities of the requestor devices is performed near the end of each operational cycle of the functional unit so that the next requestor device initiates its operational cycle immediately succeeding a current operational cycle then transacting thereby to minimize idle bus periods which would otherwise occur during arbitration cycle sequencing. When the bus is idle and only one request for access is made, the arbitration network foregoes the complete arbitration cycle and issues the grant to the requesting device thereby providing an earlier initiation of the data transfer cycle of the functional unit.

Abstract: A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus. For one element to communicate with another element, the one element, as a commanding nexus, seeks control of the interconnection and then transmits a command and address of a storage location in the other element when it receives control of the interconnection. If the command is to initiate the retrieval of information from the other element, the other element stores the command and address information in a storage file. The storage file can accumulate a number of commands and related addresses thereby to allow the different commanding nexuses to initiate similar transfers from a single one of the other elements without producing a busy indication.

Abstract: An initialization circuit for a dynamic memory element in a data processing system. The dynamic memory element comprises plural storage modules and a refreshing cycle counter that addresses individual storage locations in said modules in sequence. Address decoding circuitry normally enables a transfer with only one storage module at a time. During initialization, however, the initialization circuit forces the address decoding circuitry to identify all storage modules simultaneously and forces a data circuit to transmit a known value to the dynamic memory. All modules are thereby loaded in parallel with corresponding storage locations in each module being selected by the refreshing cycle counter.