Abstract: Methods, devices, and computer program products facilitate establishing timing synchronization between two network entities. The timing information is exchanged between a slave device and a master device at the discretion of the slave device. The exchange of timing information can, therefore, be conducted adaptively based on the needs of the salve device. The timing information is also exchanged using fewer messages, thereby reducing network traffic, reducing overhead and facilitating synchronization acquisition.

Abstract: Methods, devices, and computer program products facilitate establishing timing synchronization between two network entities. The timing information is exchanged between a slave device and a master device at the discretion of the slave device. The exchange of timing information can, therefore, be conducted adaptively based on the needs of the salve device. The timing information is also exchanged using fewer messages, thereby reducing network traffic, reducing overhead and facilitating synchronization acquisition.

Abstract: A method and system for requesting an interrupt from a host system to service an adapter connected to the host system and a data interface. Data packets, including one or more data cells, are transferred between the data interface and the host system. The host system includes a host memory that includes a plurality of memory slots to store data packets transferred between the data interface and the host system. It is determined when a transfer of data has resulted in an occurrence of an interrupt event. An interrupt event occurs when the transfer of data includes a transfer of a data cell between the data interface and the host system and the data cell is defined to be an end of a data packet. In response to the occurrence of an interrupt event, it is determined whether to generate an interrupt request to the host system.

Abstract: A mechanism for mitigating the rate at which status reports associated with raw cell data transfers occur during receive operations in a network node is presented. The network node has an adapter for coupling a network and a host system, the host system including a host memory. The adapter operates to reassemble cell data received from the network and store the reassembled cell data in the host memory. A raw report holdoff counter is programmed to count a number corresponding to a preselected rx raw report holdoff value. If a raw cell data transfer request to be processed is detected, rx raw report information necessary to creating an rx raw cell status report is copied to a temporary storage area. When the data is transferred to the host system, the raw report holdoff counter is modified by one. When the modified counter has expired, the rx raw report information is written to a report queue in host memory.

Abstract: A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.

Abstract: A mechanism for avoiding an initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller to move data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

Abstract: An apparatus and method for generating a congestion indication bit to be written to the CI field of a backwards RM ATM cell to be transmitted by a network interface utilizes a slot.sub.-- type congestion signal for indicating that the number of slots available for receiving cells is below a threshold limit, and a CI.sub.-- VC signal for indicating that the buffer space consumed by cells received on a particular VC has passed a threshold value. The CI bit in a backward RM cell for the VC when either the slot.sub.-- type congestion signal is set or the CI.sub.-- VC bit is set or the EFCI bit was set in the last data cell received by the network interface or the CI bit was set in the last forward RM cell transmitted by the network interface.

Abstract: A method of scheduling the transmission of cells from a network node involves storing entries in a schedule table at predetermined locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head, rather than the tail, of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted. The VC is therefore the first VC transmitted from the list of VCs.

Abstract: An apparatus and method for transferring data from a source memory (e.g. a host memory) to a peripheral interface via a bus utilizes a transmit buffer memory coupled to the peripheral interface, and a current time counter advancing at the rate at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table data structure stores entries in some or all of its locations, where each location corresponds to a point in time at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table pointer is used for pointing to successive locations in the schedule table. The schedule table pointer advances at a rate faster than the current time counter advances so that the schedule table pointer represents a point in time which is ahead of the point in time currently output by the current time counter.

Abstract: A mechanism by which interrupt frequency mitigation is combined with transmit raw cell status report frequency mitigation is presented. A tx raw cell status report is allowed to occur for only every N raw cell tx slots consumed. When the rate of interrupt requests is mitigated in accordance with holdoff parameters including a holdoff event count corresponding to X interrupt events and a holdoff time interval, and the raw cell status report counts as an interrupt event, an interrupt request is generated for an enabled interrupt if N*X events has occurred or the holdoff time interval has elapsed.

Abstract: A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer.

Abstract: An apparatus and method for transferring data from a source memory to a transmit buffer memory and then from the transmit buffer memory at a particular rate. A current time counter advances at the rate at which data is to be transmitted from the transmit buffer memory to the interface. A schedule memory stores entries, each valid entry being associated with data that is to be transmitted from the transmit buffer memory to the interface. A timestamp is associated with each valid entry in the schedule memory.

Abstract: A mechanism for avoiding the initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller for moving data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

Abstract: In a network node having a host system coupled to a network by an adapter, VC-specific congestion is detected and reported to the host system. The host memory includes rx slots or buffers, each corresponding to one of one or more supported slot types. Per-VC slots consumed counters are maintained to count slot consumption for each active VC. Free buffer FIFOs are maintained for each of the one or more slot types, which have a predetermined congestion threshold associated therewith. Entries in each free buffer FIFO correspond to an rx slot posted by the host system. When a new rx slot or buffer in host memory is to be allocated to an incoming cell received on a given VC, the slots consumed counter is compared to the predetermined congestion threshold. If they are equal, the VC is at threshold level and the incoming cell is discarded and a report is sent to the host system.

Abstract: A status report frequency mitigation mechanism for mitigating the frequency of status report generation for raw cells during transmit operations in a network node is presented. The status report frequency mitigation mechanism operates to adjust the frequency with which status reports for raw cells are generated by manipulating the End-of-Packet (EOP) bit in transmit slot descriptors associated with transmit slots containing raw cell data.

Abstract: An apparatus and method for scheduling data transfers between a host and adapter. A schedule table data structure resides in a memory on the adapter. Each location in the schedule table represents a point in time at which data is to be transmitted from the adapter. A current time counter advances at the rate at which data is to be transmitted from the node. A pointer points to successive locations in the schedule table, and advances through the schedule table at a rate faster than the current time counter advances so that the value stored in the pointer represents a point in time which is ahead of the point in time currently represented by the value output from the current time counter. A request for a data transfer between the host and adapter is generated when a valid entry exists at the location pointed to by the pointer. The value of the pointer at the time the request is generated is stored as the last valid time.

Abstract: In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts occurring over an interface input/output (I/O) bus, a method and apparatus which transfers all status information directly to the host memory without host involvement. The host CPU is then notified of this new status information via an interrupt. When status information is transferred to the host memory, consistency is ensured and the number of spurious interrupts are reduced. A host software driver may then read the latest status information from the interface I/O bus at its convenience any not incur any performance penalties of I/O accesses.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field, a peak rate accumulator field, and a latency accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.

Abstract: A host system and an ATM network adapter using a chaser packet are presented. The adapter receives cells over a virtual connection on the network and generates, in response to the host system, a chaser packet which allows the host to detect that all data has been transferred form the adapter buffers to host memory. When all data has been transferred, the host may release the virtual connection without data loss. The host and adapter may also transmit data. In data transmission, the chaser packet is used to determine that all data has been transmitted out onto the network before the sending host releases the virtual connection. The chaser packet is also used for resynchronization of credits where the ATM network uses credit-based flow control. The adapter uses the chaser packet to drain the local queue so that the link between the adapter and a source system may be resynchronized.