Abstract: There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.

Abstract: A detector system for high-speed Ethernet LAN is described. One embodiment includes a detector system having N one dimensional sequence detector equalizers in combination with an N-dimensional traceback decoder. The detector system detects N-dimensional symbols transmitted over N separate transport channels to N one-dimensional receivers. In one embodiment, Gigabit Ethernet receiver includes a four-wire transport to four 1D receivers and a 4D detector. The 4D detector in one embodiment is a parity code detector. In another embodiment, the 4D detector is a 4D trellis code detector.

Abstract: There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor.

Abstract: There is disclosed a mixed mode equalization system for use in a transceiver capable of operating in a high frequency Ethernet local area network (LAN).

Abstract: A transceiver according to the present invention receives data from a plurality of frequency separated transmission channels from a complementary transmitter and includes an interference filter for correcting for interference from transmitters other than the complementary transmitter. The interference filter, for example, can correct for near-end cross-talk and echo interference filtering and/or far-end crosstalk interference filtering is presented. A transceiver can include a transmitter portion and a receiver portion with one or more receivers coupled to receives signals in the plurality of frequency separated transmission channels. A baseband transmitter can be combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands).

Abstract: There is disclosed a transceiver for use in a high speed Ethernet local area network (LAN). The transceiver comprises: 1) front-end analog signal processing circuitry comprising: a) a line driver for transmitting an outgoing analog signal to an external cable; b) a DC offset correction circuit for reducing a DC component in an incoming analog signal; c) an echo canceller; d) an automatic gain control (AGC) circuit; and e) an adaptive analog equalization filter. The transceiver also comprises: 2) an analog-to-digital converter (ADC) for converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising: a) a digital finite impulse response (FIR) filter; b) a digital echo cancellation circuit to produce a reduced-echo incoming digital signal; c) a digital automatic gain control (AGC) circuit; and d) a digital base line wander circuit.

Abstract: State machines are disclosed for establishing a communication channel between communication devices, such as for example, between two modems in a backplane environment. In accordance with one embodiment, a start-up state machine employs the full data rate signaling scheme of the communication device to initiate a communication channel between two communication devices. By sending predefined bit patterns using the existing signaling scheme, the communication devices can determine the state of each other, establish a communication link, and determine when the communication of data or other desired information can occur.

Abstract: A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Abstract: A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. Additionally, a cross-channel interference filter in a receiver section corrects for cross-channel interference in the communication system. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: Disclosed are systems and methods for monitoring and controlling operating modes in a network transceiver. In one embodiment, a computer system is associable with an Ethernet network, and comprises a processing unit, a memory and a transceiver. The transceiver comprises an encoder, a decoder and a controller. The controller controls operating modes of the transceiver, and, specifically, (i) negotiates a communications channel between the computer system and another computer system over the Ethernet network wherein the computer system enters one of a master state and a slave state, and (ii) repeatedly directs, in response to entering the master state or slave state, the encoder to encode data to be transmitted to the another computer in one of an industry-compliant mode and a custom mode until the encoded data is properly received by the other computer.