Patents by Inventor Peter J. Sorce
Peter J. Sorce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10535592Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.Type: GrantFiled: March 26, 2018Date of Patent: January 14, 2020Assignee: International Business Machines CorporationInventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
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Patent number: 10168477Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: GrantFiled: November 17, 2016Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Patent number: 10168478Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: GrantFiled: March 23, 2017Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Publication number: 20180218971Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.Type: ApplicationFiled: March 26, 2018Publication date: August 2, 2018Inventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
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Publication number: 20180218970Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.Type: ApplicationFiled: March 26, 2018Publication date: August 2, 2018Inventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
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Patent number: 9953908Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.Type: GrantFiled: October 30, 2015Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
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Patent number: 9872394Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.Type: GrantFiled: April 5, 2016Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
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Publication number: 20170192172Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: ApplicationFiled: March 23, 2017Publication date: July 6, 2017Inventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Publication number: 20170125329Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
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Patent number: 9632251Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: GrantFiled: April 2, 2014Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Publication number: 20170068050Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Inventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Patent number: 9433101Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.Type: GrantFiled: October 16, 2014Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
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Publication number: 20160219715Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
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Publication number: 20160113119Abstract: A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.Type: ApplicationFiled: October 16, 2014Publication date: April 21, 2016Inventors: Steven A. Cordes, Bing Dang, Sung K. Kang, Yu Luo, Peter J. Sorce
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Patent number: 9171742Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: GrantFiled: July 22, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
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Publication number: 20150285998Abstract: According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aydin Babakhani, Steven A. Cordes, Jean-Olivier Plouchart, Scott K. Reynolds, Peter J. Sorce, Robert E. Trzcinski
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Publication number: 20150024549Abstract: The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.Type: ApplicationFiled: July 22, 2013Publication date: January 22, 2015Applicant: International Business Machines CorporationInventors: Evan G. Colgan, Steven A. Cordes, Daniel C. Edelstein, Vijayeshwar D. Khanna, Kenneth Latzko, Qinghuang Lin, Peter J. Sorce, Sri M. Sri-Jayantha, Robert L. Wisnieff, Roy R. Yu
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Patent number: 8388782Abstract: A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.Type: GrantFiled: May 27, 2010Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Paul S. Andry, Bing Dang, John Knickerbocker, Aparna Prahbakar, Peter J. Sorce, Robert E. Trzcinski, Cornelia K. Tsang
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Patent number: 5231751Abstract: This invention relates generally to a structure and process for thin film interconnect, and more particularly to a structure and process for a multilayer thin film interconnect structure with improved dimensional stability and electrical performance. The invention further relates to a process of fabrication of the multilayer thin film structures. The individual thin film structure is termed a compensator, and functions as both a ground/reference plane and as a stabilizing entity with regard to dimensional integrity. The compensator is comprised primarily of a metal sheet having a metallized via pattern and high-temperature stable polymer as an insulator.Type: GrantFiled: October 29, 1991Date of Patent: August 3, 1993Assignee: International Business Machines CorporationInventors: Krishna G. Sachdev, Benedikt M. J. Kellner, Kathleen M. McGuire, Peter J. Sorce