Abstract: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.

Abstract: A resistive memory device. Implementations may include an array of memory cells including resistive memory elements which are coupled to isolation transistors and which may include a magnetic tunnel junction. A decoder decodes input address information to select a row of the array. A binarizer coupled to the memory array assigns binary weights to outputs of the memory array output through bit lines coupled to the memory cells. A summer sums the binary weighted outputs, and a quantizer generates an output digital code corresponding to data stored in a plurality of memory cells during a prior program cycle. The outputs of the memory array may be currents or voltages. In implementations multiple arrays of memory cells may be utilized and their respective outputs combined to form higher bit outputs, such as eight bit, twelve bit, sixteen bit, and so forth.

Abstract: A magnetoresistive multi-level generator including a first series circuit with a first magnetoresistive element having a resistance equal to Rmax connected in series with n first magnetoresistive elements each having a resistance equal to Rmin. Where n is equal to a whole integer greater than one, n additional series circuits, each including an additional magnetoresistive element with a resistance equal to Rmax connected in series with n magnetoresistive elements each with a resistance equal to Rmin. The first and n additional series circuits being connected in series between the input and output terminals and in parallel with each other. Whereby a total resistance between the input and output terminals is a level Rmin+&Dgr;R/n, where &Dgr;R is equal to Rmax−Rmin.

Abstract: Processing equipment with embedded MRAMs, and a method of fabricating, including a data processing device fabricated on a semiconductor chip with MRAM cells fabricated on the chip to form one to all of the memories on the chip. Also included is a dual bank memory in communication with the data processing device and circuitry coupled to the data processing device and the dual bank memory for providing simultaneous read access to the dual bank memory.

Abstract: A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.

Abstract: A magnetoresistive multi-level generator including a first series circuit with a first magnetoresistive element having a resistance equal to Rmax connected in series with n first magnetoresistive elements each having a resistance equal to Rmin. Where n is equal to a whole integer greater than one, n additional series circuits, each including an additional magnetoresistive element with a resistance equal to Rmax connected in series with n magnetoresistive elements each with a resistance equal to Rmin. The first and n additional series circuits being connected in series between the input and output terminals and in parallel with each other. Whereby a total resistance between the input and output terminals is a level Rmin+&Dgr;R/n, where &Dgr;R is equal to Rmax−Rmin.

Abstract: A non-volatile, bistable magnetic tunnel junction (MTJ) register cell includes first and second magnetic tunnel junctions connected for differential operation. The first MTJ is coupled between an easy axis line and an output terminal and the second MTJ is coupled between an inverse easy axis line and an inverse output terminal. A hard axis line is coupled magnetically to the MTJs and an enable line is coupled to the MTJs for enabling and disabling the differential operation. The MTJ register cell can be connected as a PIPO non-volatile register, a right or left non-volatile shift register, or a multi-bit bi-directional non-volatile shift register.

Abstract: A magnetoresistive random access memory architecture free of isolation devices includes a plurality of data columns of non-volatile magnetoresistive elements. A reference column includes non-volatile magnetoresistive elements positioned adjacent to the data column. Each column is connected to a current conveyor. A selected data current conveyor and the reference current conveyor are connected to inputs of a differential amplifier for differentially comparing a data voltage to a reference voltage. The current conveyors are connected directly to the ends of the data and reference bitlines. This specific arrangement allows the current conveyors to be clamped to the same voltage which reduces or removes sneak circuits to substantially reduce leakage currents.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2)(1+Rmin/Rmax), where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell. A reference voltage generator is disclosed which generates the reference voltage and includes an operational amplifier and two MTJ memory cells connected to provide an output signal equal to (Vbias1/2)(1+Rmin/Rmax).

Abstract: A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.

Abstract: A non-volatile, bistable magnetic tunnel junction cache memory including a cache tag array and a cache data array. The cache tag array includes non-volatile magnetic memory tag cells arranged in rows and columns. Each row of the tag array includes a word line and a digit line associated with each tag cell in the row. The cache data array includes non-volatile magnetic memory data cells arranged in rows and columns. The rows of the data array correspond with the rows of the tag array and each row of the data array is magnetically associated with the word line and the digit line associated with each corresponding row of the tag array.

Abstract: The MRAM architecture includes a data column of memory cells and a reference column, including a midpoint generator, positioned adjacent the data column on a substrate. The memory cells and the midpoint generator include similar magnetoresistive memory elements, e.g. MTJ elements. The MTJ elements of the generator are each set to one of Rmax and Rmin and connected together to provide a total resistance of a midpoint between Rmax and Rmin. A differential read-out circuit is coupled to the data column and to the reference column for differentially comparing a data voltage to a reference voltage.

Abstract: A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2) (1+Rmin/Rmax), where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell.

Abstract: A non-volatile, bistable magnetic tunnel junction (MTJ) register cell includes first and second magnetic tunnel junctions connected for differential operation. The first MTJ is coupled between an easy axis line and an output terminal and the second MTJ is coupled between an inverse easy axis line and an inverse output terminal. A hard axis line is coupled magnetically to the MTJs and an enable line is coupled to the MTJs for enabling and disabling the differential operation. The MTJ register cell can be connected as a PIPO non-volatile register, a right or left non-volatile shift register, or a multi-bit bi-directional non-volatile shift register.

Abstract: A magnetoresistive memory fabricated on a common substrate. The memory including first and second spaced apart magnetoresistive memory arrays each including a plurality of MTJ memory cells arranged in rows and columns and a plurality of word/digit lines associated with the rows of magnetoresistive memory cells of each of the arrays. Switching circuitry is positioned on the substrate between the first and second arrays and designed to select a word/digit line in one of the first and second arrays. A current source is positioned on the substrate adjacent and coupled to the switching circuitry for supplying programming current to the selected word/digit line.

Abstract: A magnetoresistive midpoint generator includes an input and an output terminal and four non-volatile magnetoresistive elements. Each element is programmable into a resistance equal to one of Rmax and Rmin, where Rmin is a minimum resistive value corresponding to parallel states of magnetization and Rmax is a maximum resistive value corresponding to anti-parallel states of magnetization. First and second series circuits, each series circuit including a magnetoresistive element with a resistance equal to Rmax connected in series with a magnetoresistive element with a resistance equal to Rmin, are connected in parallel between the input and output terminals, whereby a total resistance between the input and output terminals is a midpoint between Rmax and Rmin.

Abstract: Readout circuitry for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2) (1+Rmin/Rmax) where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell, and Rmax is a maximum resistance of the magnetic tunneling junction memory cell.

Abstract: A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.

Abstract: Magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns and each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.