Patents by Inventor Peter Kanschat
Peter Kanschat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978700Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.Type: GrantFiled: July 25, 2022Date of Patent: May 7, 2024Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Publication number: 20220359365Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 11437311Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.Type: GrantFiled: November 18, 2020Date of Patent: September 6, 2022Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Publication number: 20210074624Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 10867902Abstract: A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices.Type: GrantFiled: December 14, 2018Date of Patent: December 15, 2020Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Publication number: 20190189553Abstract: A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices.Type: ApplicationFiled: December 14, 2018Publication date: June 20, 2019Inventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 9984928Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.Type: GrantFiled: December 14, 2016Date of Patent: May 29, 2018Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Peter Kanschat
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Patent number: 9891247Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.Type: GrantFiled: September 26, 2014Date of Patent: February 13, 2018Assignee: Infineon Technologies AGInventors: Peter Kanschat, Thilo Stolze
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Patent number: 9818730Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.Type: GrantFiled: September 4, 2014Date of Patent: November 14, 2017Assignee: Infineon Technologies AGInventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
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Patent number: 9620459Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.Type: GrantFiled: September 3, 2014Date of Patent: April 11, 2017Assignee: Infineon Technologies AGInventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
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Publication number: 20170098580Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.Type: ApplicationFiled: December 14, 2016Publication date: April 6, 2017Inventors: Olaf Hohlfeld, Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Peter Kanschat
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Patent number: 9589859Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.Type: GrantFiled: August 19, 2014Date of Patent: March 7, 2017Assignee: Infineon Technologies AGInventors: Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
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Patent number: 9559065Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.Type: GrantFiled: September 3, 2014Date of Patent: January 31, 2017Assignee: Infineon Technologies AGInventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
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Patent number: 9543389Abstract: A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the semiconductor body. A control structure electrically connects a recombination region to the drift zone during a desaturation cycle and disconnects the recombination region from the drift zone outside the desaturation cycle. During the desaturation cycle the recombination region reduces a charge carrier plasma in the drift zone and reduces reverse recovery losses without adversely affecting blocking characteristics.Type: GrantFiled: December 11, 2013Date of Patent: January 10, 2017Assignee: Infineon Technologies AGInventors: Johannes Georg Laven, Roman Baburske, Peter Kanschat
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Publication number: 20150162407Abstract: A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the semiconductor body. A control structure electrically connects a recombination region to the drift zone during a desaturation cycle and disconnects the recombination region from the drift zone outside the desaturation cycle. During the desaturation cycle the recombination region reduces a charge carrier plasma in the drift zone and reduces reverse recovery losses without adversely affecting blocking characteristics.Type: ApplicationFiled: December 11, 2013Publication date: June 11, 2015Inventors: Johannes Georg Laven, Roman Baburske, Peter Kanschat
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Publication number: 20150091551Abstract: A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.Type: ApplicationFiled: September 26, 2014Publication date: April 2, 2015Inventors: Peter Kanschat, Thilo Stolze
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Patent number: 8994413Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.Type: GrantFiled: April 26, 2013Date of Patent: March 31, 2015Assignee: Infineon Technologies AGInventors: Peter Kanschat, Andre Arens, Hartmut Jasberg, Ulrich Schwarzer
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Publication number: 20150061144Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.Type: ApplicationFiled: September 3, 2014Publication date: March 5, 2015Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
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Publication number: 20150061100Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.Type: ApplicationFiled: September 4, 2014Publication date: March 5, 2015Inventors: Gottfried Beer, Irmgard Escher-Poeppel, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat
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Publication number: 20150054166Abstract: A semiconductor arrangement includes a plurality of chip assemblies, each of which includes a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally circumferentially in a ring-shaped fashion such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.Type: ApplicationFiled: August 19, 2014Publication date: February 26, 2015Inventors: Gottfried Beer, Edward Fuergut, Juergen Hoegerl, Olaf Hohlfeld, Peter Kanschat