Patents by Inventor Peter M. Held

Peter M. Held has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11163574
    Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task and storing the task-relating branch prediction data of the second task in the branch prediction history table.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
  • Patent number: 11099851
    Abstract: Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Martin Schwidefsky
  • Patent number: 10684857
    Abstract: A method includes storing a first address of a first instruction executed by a processor core in a first table, where the first instruction writes a value into a register for utilization in addressing memory. The method stores the first address of the first instruction executed by the processor core in a second table with multiple entries, where a register value loaded into the register is utilized as a second address by a second instruction executed by the processor core to access a main memory. The method determines whether an instruction address associated with an instruction executed by the processor core is present in the second table, where the instruction address is the second address. Responsive to determining the instruction address is present in the second table, the method prefetches data from the main memory, where the register value is utilized as the second address in the main memory.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: Wolfgang Gellerich, Gerrit Koch, Peter M. Held, Martin Schwidefsky
  • Publication number: 20200133678
    Abstract: Examples of techniques for branch prediction for indirect branch instructions are described herein. An aspect includes detecting a first register setting instruction in an instruction pipeline of a processor, wherein the first register setting instruction stores a target instruction address in a first register of the processor. Another aspect includes looking up the first register setting instruction in a first table. Another aspect includes, based on there being a hit for the first register setting instruction in the first table, determining instruction address data corresponding to a first indirect branch instruction that is associated with the first register setting instruction in a first entry in the first table. Another aspect includes updating a branch prediction for the first indirect branch instruction in a branch prediction logic of the processor based on the target instruction address.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Martin Schwidefsky
  • Patent number: 10489296
    Abstract: Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Peter M. Held, Gerrit Koch, Christoph Raisch, Martin Schwidefsky
  • Publication number: 20190354372
    Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task and storing the task-relating branch prediction data of the second task in the branch prediction history table.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
  • Patent number: 10430194
    Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
  • Patent number: 10423418
    Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
  • Publication number: 20190235872
    Abstract: A method includes storing a first address of a first instruction executed by a processor core in a first table, where the first instruction writes a value into a register for utilization in addressing memory. The method stores the first address of the first instruction executed by the processor core in a second table with multiple entries, where a register value loaded into the register is utilized as a second address by a second instruction executed by the processor core to access a main memory. The method determines whether an instruction address associated with an instruction executed by the processor core is present in the second table, where the instruction address is the second address. Responsive to determining the instruction address is present in the second table, the method prefetches data from the main memory, where the register value is utilized as the second address in the main memory.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Wolfgang Gellerich, Gerrit Koch, Peter M. Held, Martin Schwidefsky
  • Publication number: 20180081813
    Abstract: Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: WOLFGANG GELLERICH, PETER M. HELD, GERRIT KOCH, CHRISTOPH RAISCH, MARTIN SCHWIDEFSKY
  • Publication number: 20180081814
    Abstract: Embodiments here relate to managing a cache by exploiting a cache line hierarchy is provided. Managing the cache includes reading cache references of a first task from a cache reference save area of a first task data structure in response to a context switch. Further, managing the cache includes prefetching and restoring cache lines of the first task to the cache based on the cache references. Note that the cache lines can be predetermined from a plurality of cache lines associated with the first task during an extraction operation with respect to the first task and the cache line hierarchy.
    Type: Application
    Filed: February 23, 2017
    Publication date: March 22, 2018
    Inventors: WOLFGANG GELLERICH, PETER M. HELD, GERRIT KOCH, CHRISTOPH RAISCH, MARTIN SCHWIDEFSKY
  • Publication number: 20170153895
    Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum
  • Publication number: 20170153893
    Abstract: A method for managing tasks in a computer system comprising a processor and a memory, the method includes performing a first task by the processor, the first task comprising task-relating branch instructions and task-independent branch instructions and executing the branch prediction method, the execution resulting in task-relating branch prediction data in the branch prediction history table. In response to determining that the first task is to be interrupted or terminated, the method includes storing the task-relating branch prediction data of the first task in the task structure of the first task. In response to determining that a second task is to be continued, the method includes reading task-relating branch prediction data of the second task from the task structure of the second task, storing the task-relating branch prediction data of the second task in the branch prediction history table, and ensuring that task-independent branch prediction data is maintained.
    Type: Application
    Filed: March 10, 2016
    Publication date: June 1, 2017
    Inventors: Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky, Chung-Lung K. Shum