Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another with broadcast of instructions to selected groups of units controlled by a controlling processor. The coupling of the processing elements logic enables dynamic mode assignment and dynamic mode switching, allowing processors operating in a SIMD mode to make maximum memory and cycle time usage. On and instruction by instruction level basis, modes can be switched from SIMD to MIMD, and even into SISD mode on the controlling processor for inherently sequential computation allowing a programmer or complier to build a program for the computer system which uses the optimal kind of parallelism (SISD, SIMD, MIMD).

Abstract: A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

Abstract: A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation.

Abstract: An improved checkpoint retry mechanism is disclosed which automatically updates checkpoint addresses to enable the retry of instruction sequences for shorter segments of recently executed code, in response to the detection of an error since the passage of the current checkpoint. It does this by updating three different types of checkpoint addresses, a first checkpoint address for the instruction which follows a memory write or I/O write operation, a second type checkpoint address for the first instruction in an interrupt service routine, and a third type checkpoint address for the first instruction in an interrupted routine following an interrupt event. The resulting checkpoint retry mechanism is more efficient and faster because it adaptively updates the checkpoint address to reduce the size of code segments which must be reexecuted during retry operations. The invention operates to avoid memory corruption and erroneous I/O outputs during retry operations and protects from erroneous retry sequences.

Abstract: An address generator for an M-interleaved memory for accessing row or column elements of a matrix stored in a skewed matrix pattern includes an apparatus for circularly shifting the addresses for the i.sup.th row of a matrix by s(i-1) positions so that both row and column elements of the matrix can be accessed at the same access rate. In other words, apparatus is provided for circularly generating the sequences of appropriate memory addresses for the desired row or column elements so that either the row or column elements can be accessed at the memory system's maximum access rate. The apparatus includes a base register having an input connected to a first adder which adds an input value A to the contents in the base register for storing the output of the adder as a pointer to the beginning of the current row of the matrix in the memory to be accessed.