Abstract: A switch device may comprise a micro-relay disposed between a first terminal and a second terminal. The micro-relay may be configured to selectively electrically couple the first terminal to the second terminal. The switch device may further comprise a bypass circuit configured to selectively divert at least a portion of electrical current flowing from the first terminal to the micro-relay, and direct the diverted electrical current to the second terminal. The switch device may further comprise an energy harvesting circuit configured to (i) withdraw a portion of energy flowing into the switch device, (ii) store the portion of energy in an energy storage device, and (iii) supplying the energy stored in the energy storage device to one or more components within the switch device.

Abstract: The present subject matter relates to devices, systems, and methods for controlling an array of two-state elements that can be independently positioned in either first state or a second state. A non-volatile memory in communication with the plurality of two-state elements is configured to receive an input digital control word that addresses a location within the non-volatile memory and to output one of a plurality of array control words stored at the location addressed within the memory to the plurality of two-state elements, wherein the array control word sets a predetermined combination of the plurality of two-state elements to be in the first state and in the second state, and wherein the predetermined combination of the plurality of two-state elements in the first state and in the second state optimally achieves a desired behavior of the array corresponding to the input digital control word.

Abstract: A system and method for networking a plurality of nodes is disclosed. A network of data devices having data representations of connectivity, network node position, and/or position topologies is also disclosed, wherein the network may be self-configuring and the network nodes spatially addressable. In another embodiment, a unique form of signal acquisition assistance intrinsic in the signal structure may also be used. A data positioning device capable of operating as a node in a network of the present invention is also disclosed.

Abstract: A system and method for networking a plurality of nodes is disclosed. A network of data devices having data representations of connectivity, network node position, and/or position topologies is also disclosed, wherein the network may be self-configuring and the network nodes spatially addressable. In another embodiment, a unique form of signal acquisition assistance intrinsic in the signal structure may also be used. A data positioning device capable of operating as a node in a network of the present invention is also disclosed.

Abstract: A GPS enabled timepiece. A timepiece in accordance with the present invention comprises a GPS receiver, wherein the GPS receiver is modified to operate in a timekeeping environment, a timepiece, coupled to the GPS receiver, wherein the GPS receiver provides time updates to the timepiece, and a display, coupled to the timepiece, wherein the GPS-updated time of the timepiece is displayed.

Abstract: A network, network device and method is disclosed. In one embodiment, a method includes transmitting communication signals from a first network node to a second network node, where the first and second network nodes comprise a network and each include a receiver portion and a transponder portion. The method further comprises receiving, by the first and second network nodes, position signals from a plurality of navigation beacons, and generating transmitter codes for the transponder portions using local code generators of the receiver portions.

Abstract: A method and apparatus for collocating an interface circuit with a disk drive read/write head is described. In one embodiment the interface circuit is attached to the load arm on one side and the miniflex interconnect on the other. The read/write head is mounted on the miniflex directly below the interface circuit. The interface circuit comprises a read signal preamplifier, a write driver, and head selection circuitry. A common multiplexer circuit is used to perform the other conventional read/write circuit functions. The common multiplexer circuit includes a head selection block to determine which heads are activated, a head driver block, and a read receiver block. The common multiplexer circuit is mounted at the base of the miniflex.

Abstract: A method and apparatus for collocating an interface circuit with a disk drive read/write head is described. In one embodiment the interface circuit is attached to the load arm on one side and the miniflex interconnect on the other. The read/write head is mounted on the miniflex directly below the interface circuit. The interface circuit comprises a read signal preamplifier, a write driver, and head selection circuitry. A common multiplexer circuit is used to perform the other conventional read/write circuit functions. The common multiplexer circuit includes a head selection block to determine which heads are activated, a head driver block, and a read receiver block. The common multiplexer circuit is mounted at the base of the miniflex.

Abstract: A method and apparatus for collocating an interface circuit with a disk drive read/write head is described. In one embodiment the interface circuit is attached to the load arm on one side and the miniflex interconnect on the other. The read/write head is mounted on the miniflex directly below the interface circuit. The interface circuit comprises a read signal preamplifier, a write driver, and head selection circuitry. A common multiplexer circuit is used to perform the other conventional read/write circuit functions. The common multiplexer circuit includes a head selection block to determine which heads are activated, a head driver block, and a read receiver block. The common multiplexer circuit is mounted at the base of the miniflex.

Abstract: Method and apparatus for generating a decode window. A phase locked loop locks a pulse edge of a delayed read data (DRD) signal to an edge of a voltage control oscillator (VCO) clock signal. The edges of the decode window are generated directly from the outer edges of the VCO clock signal. This eliminates errors introduced by quarter cell delay lines, particularly in integrated circuit applications. The transition of the VCO clock signal is used to define a nominal center position coinciding with the mean center position of a data stream. Differential control signals are utilized to shift the VCO transition so that it may be synchronized with the mean bit center position and compensate for non-symmetrical peak jitter. The VCO transition may be shifted without changing the period of the VCO clock signal.