Abstract: An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.

Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.

Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Abstract: In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device.

Abstract: An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.

Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors.

Abstract: An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.

Abstract: An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.

Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.

Abstract: In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.

Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.

Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.

Abstract: A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×1015 atoms/cm3.

Abstract: In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device.

Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.