Patents by Inventor Peter Ossimitz
Peter Ossimitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10090251Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.Type: GrantFiled: July 24, 2015Date of Patent: October 2, 2018Assignee: Infineon Technologies AGInventors: Peter Ossimitz, Gottfried Beer, Juergen Hoegerl, Andreas Munding
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Patent number: 9871017Abstract: Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.Type: GrantFiled: January 4, 2016Date of Patent: January 16, 2018Assignee: Infineon Technologies AGInventors: Peter Ossimitz, Tobias Jacobs
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Patent number: 9859251Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.Type: GrantFiled: February 1, 2016Date of Patent: January 2, 2018Assignee: Infineon Technologies AGInventors: Gottfried Beer, Peter Ossimitz
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Publication number: 20170194288Abstract: Representative implementations of devices and techniques provide optimized electrical performance of interconnectivity components of multi-layer integrated circuits (IC) such as chip dice, for example. Different layers of the multi-layer IC include contact terminals that may be used to connect to circuits, systems, and carriers external to the IC.Type: ApplicationFiled: January 4, 2016Publication date: July 6, 2017Inventors: Peter OSSIMITZ, Tobias JACOBS
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Patent number: 9651630Abstract: The disclosure relates to a circuitry including a first contact connected to a power supply, a first compare unit connected to the first contact and to a first reference signal, wherein the first compare unit is configured to compare a voltage at the first contact with the first reference signal and provide a first output signal for further processing.Type: GrantFiled: July 17, 2013Date of Patent: May 16, 2017Assignee: Infineon Technologies AGInventors: Jens Barrenscheen, Roderick McConnell, Peter Ossimitz
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Publication number: 20170025357Abstract: A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.Type: ApplicationFiled: July 24, 2015Publication date: January 26, 2017Inventors: Peter Ossimitz, Gottfried Beer, Juergen Hoegerl, Andreas Munding
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Publication number: 20160225745Abstract: A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.Type: ApplicationFiled: February 1, 2016Publication date: August 4, 2016Inventors: Gottfried Beer, Peter Ossimitz
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Patent number: 9385059Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.Type: GrantFiled: August 28, 2013Date of Patent: July 5, 2016Assignee: Infineon Technologies AGInventors: Peter Ossimitz, Juergen Schaefer, Liu Chen, Markus Dinkel, Stefan Macheiner
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Patent number: 9362187Abstract: A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.Type: GrantFiled: January 18, 2013Date of Patent: June 7, 2016Assignee: Infineon Technologies AGInventor: Peter Ossimitz
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Patent number: 9299673Abstract: Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.Type: GrantFiled: May 28, 2014Date of Patent: March 29, 2016Assignee: Infineon Technologies AGInventors: Peter Ossimitz, Matthias Von Daak, Dirk Hesidenz
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Patent number: 9219031Abstract: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.Type: GrantFiled: May 13, 2013Date of Patent: December 22, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Peter Ossimitz, Robert Bauer, Tobias Jacobs
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Patent number: 9204543Abstract: An Integrated Circuit (IC) package comprises a package comprising a first set of pads having a pinout that is compatible with a chip core of a product family. A second set of pads are on substantially the same plane as the first set of pads and outside the package core. The second set of pads is configured to accommodate a circuit outside the chip core. The geometric center of the package core is different from the geometric center of the IC package.Type: GrantFiled: December 3, 2013Date of Patent: December 1, 2015Assignee: Infineon Technologies AGInventor: Peter Ossimitz
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Patent number: 9082644Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.Type: GrantFiled: January 18, 2013Date of Patent: July 14, 2015Assignee: Infineon Technologies AGInventors: Peter Ossimitz, Matthias von Daak, Gottfried Beer
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Publication number: 20150156872Abstract: An Integrated Circuit (IC) package comprises a package comprising a first set of pads having a pinout that is compatible with a chip core of a product family. A second set of pads are on substantially the same plane as the first set of pads and outside the package core. The second set of pads is configured to accommodate a circuit outside the chip core. The geometric center of the package core is different from the geometric center of the IC package.Type: ApplicationFiled: December 3, 2013Publication date: June 4, 2015Applicant: Infineon Technologies AGInventor: Peter OSSIMITZ
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Publication number: 20150062825Abstract: An electronic device comprises a substrate, at least one electronic chip mounted on and electrically connected to the substrate and being configured as a system control unit for controlling a connected system, a heat removal structure thermally connected to the at least one electronic chip and configured for removing heat generated by the at least one electronic chip upon operation of the electronic device, and an overmolding structure configured for at least partially encapsulating at least the at least one electronic chip and the substrate.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Inventors: Peter Ossimitz, Juergen Schaefer, Liu Chen, Markus Dinkel, Stefan MacHeiner
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Publication number: 20150022924Abstract: The disclosure relates to a circuitry including a first contact connected to a power supply, a first compare unit connected to the first contact and to a first reference signal, wherein the first compare unit is configured to compare a voltage at the first contact with the first reference signal and provide a first output signal for further processing.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Jens Barrenscheen, Roderick McConnell, Peter Ossimitz
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Publication number: 20140332953Abstract: A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least one bonding pad of a majority of the plurality of electrical nets, wherein the plurality of pillars may be configured to connect the at least one bonding pad of the majority of the plurality of electrical nets to a chip-external connection region.Type: ApplicationFiled: May 13, 2013Publication date: November 13, 2014Applicant: Infineon Technologies AGInventors: Peter Ossimitz, Robert Bauer, Tobias Jacobs
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Publication number: 20140264814Abstract: Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: Infineon Technologies AGInventors: Peter Ossimitz, Matthias Van Daak, Dirk Hesidenz
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Patent number: 8799704Abstract: A method for correcting faults in semiconductor memory components provides an application system having a multichip module (1) which has a semiconductor memory component (2) containing a volatile memory and a diverting circuit (7). When the application system is being booted up, addresses of faulty memory cells in the semiconductor memory component (2) are loaded into the multichip module (1), with the result that the diverting circuit (7) diverts access to a memory cell in the replacement data memory if a faulty memory cell in the semiconductor memory component (2) is accessed.Type: GrantFiled: March 29, 2007Date of Patent: August 5, 2014Assignee: Infineon Technologies AGInventor: Peter Ossimitz
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Publication number: 20140203278Abstract: A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip. The first and second groups of terminal pads are arranged on a common terminal surface of the chip package. A pad size of a terminal pad of the first group of terminal pads is greater than a pad size of a terminal pad of the second group of terminal pads.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: INFINEON TECHNOLOGIES AGInventor: Peter Ossimitz