Abstract: A bit synchronizer (16) that includes a tapped delay line (38) connected to a plurality of timing hypothesis circuits. A control and adjudication circuit (50) is connected to the timing hypothesis circuits, and compares outputs of the timing hypothesis circuits and selects one. Each of the timing hypothesis circuits includes a sum-and-dump summer (112) that is connected to outputs of the tapped delay line (38). The timing hypothesis circuits further include an absolute value circuit (46) and an averaging circuit (48). A select switch (60) is connected to the summers (112) and receives a switch control signal from the control and adjudication circuit (50). A threshold test circuit (62) compares the selected output signal to a threshold value and outputs a mark or space symbol.

Abstract: A bit synchronizer for a digital receiver system accounts for loss of bit synchronization due to transmission phenomena. The bit synchronizer includes a DC level estimator for converting a sampled digital signal having a bit rate and a sampling rate into a level-adjusted signal. A delay module generates a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The timing signals correspond to early, on-time, and late sampling windows. The control module generates an output signal based on the timing signals such that the transmit and receive bit timing are synchronized. In one embodiment, the control module has an absolute value stage, an integration stage, and a signal selector. The signal selector is able to select between the timing signals, adjust the symbol rate to re-center the on-time gate, and memory swap to maintain correct averaging operations.

Abstract: A bit synchronizer for a digital receiver system accounts for loss of bit synchronization due to received noise, signal fading, relative time drift, time jitter, and other transmission phenomena. The bit synchronizer (10) includes a DC level estimator (12) for converting a sampled digital signal having a bit rate and a sampling rate into a level-adjusted signal. A delay module (14) generates a first timing signal, a second timing signal, and a third timing signal based on the level-adjusted signal. The timing signals correspond to early, on-time, and late sampling windows. The control module (16) generates an output signal based on the timing signals such that the transmit and receive bit timing are synchronized. In one embodiment, the control module (16) has an absolute value stage (36), an integration stage (38), and a signal selector (40).

Abstract: A photonic interconnect and photonic processing apparatus (10) for use in a communication and data handling satellite (12) is disclosed. The photonic interconnect and photonic processing apparatus (10) includes a receiving device (14) for receiving a plurality of input RF signals. An optical conversion device (28) coupled to the receiving device (14) converts the plurality of input RF signals to a plurality of input optical signals. This plurality of input optical signals are coupled to a plurality of input optical fibers (30). A distribution device (32) optically coupled to the optical conversion device (28) distributes at least one output optical signal from the plurality of input optical signals coupled to the plurality of input optical fibers.