Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

Abstract: The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

Abstract: The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

Abstract: A device includes a first epitaxial layer, a second epitaxial layer, an interlayer, a gate dielectric layer, and a gate layer. The interlayer is between the first epitaxial layer and the second epitaxial layer. The gate dielectric layer is around the interlayer. The gate layer is around the gate dielectric layer and the interlayer. The interlayer is slanted with respect to a sidewall of the gate layer.

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

Abstract: A method for manufacturing a semiconductor structure including forming a first type semiconductor layer. The method also includes forming a semiconductor interlayer over the first type semiconductor layer. The method further includes forming a second type semiconductor layer over the semiconductor interlayer. The method further includes etching the first type semiconductor layer, the semiconductor interlayer, and the second type semiconductor layer to form a fin structure. The method further includes oxidizing the semiconductor interlayer.

Abstract: A method includes forming a first epitaxial layer having a first dopant over a substrate; etching the first epitaxial layer to form a fin with a polar sidewall; and forming in sequence a semiconductor interlayer and a second epitaxial layer to surround the fin, in which the second epitaxial layer has a second dopant with a different conductivity type than the first dopant.

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

Abstract: A method includes forming a first epitaxial layer having a first dopant over a substrate; etching the first epitaxial layer to form a fin with a polar sidewall; and forming in sequence a semiconductor interlayer and a second epitaxial layer to surround the fin, in which the second epitaxial layer has a second dopant with a different conductivity type than the first dopant.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.

Abstract: The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

Abstract: A method for manufacturing a semiconductor structure including forming a first type semiconductor layer. The method also includes forming a semiconductor interlayer over the first type semiconductor layer. The method further includes forming a second type semiconductor layer over the semiconductor interlayer. The method further includes etching the first type semiconductor layer, the semiconductor interlayer, and the second type semiconductor layer to form a fin structure. The method further includes oxidizing the semiconductor interlayer.

Abstract: A device includes a first epitaxial layer, a second epitaxial layer, an interlayer, a gate dielectric layer, and a gate layer. The interlayer is between the first epitaxial layer and the second epitaxial layer. The gate dielectric layer is around the interlayer. The gate layer is around the gate dielectric layer and the interlayer. The interlayer is slanted with respect to a sidewall of the gate layer.

Abstract: A tunnel field-effect transistor (TFET), comprising a first source/drain layer comprising a first polar sidewall; a second source/drain layer surrounding the first source/drain layer, wherein the second source/drain layer and the first source/drain layer are of opposite conductivity types; and a semiconductor interlayer between the second source/drain layer and first polar sidewall of the first source/drain layer.

Abstract: A device includes a first semiconductor layer, a second semiconductor layer, and an intrinsic semiconductor layer. The second semiconductor layer is over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of opposite conductivity types. The second semiconductor layer includes a first sidewall and a second sidewall substantially perpendicular to and larger than the first sidewall. The intrinsic semiconductor layer is in contact with the second sidewall of the second semiconductor layer and the first semiconductor layer.

Abstract: The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer.