Abstract: An anti-polishing ring (143) formed to be integral with the cylinder head (132) of a diesel locomotive engine (120). A top portion (140) of a piston (128) of the engine is received by a skirt portion (142) of the cylinder head. The skirt portion has a diameter D4 that is greater than the piston diameter D3 but more than the diameter D1 of a cylinder liner (126). A coolant passage (148) may be formed in the cylinder head proximate the integral anti-polishing ring.

Abstract: A cutter drum for a web-cutting machine has a body having a cylindrical outer surface centered on an axis and formed with at least one seat having a radially outwardly directed floor face extending axially and helically of the axis and a tangentially directed rear face extending generally radially of the axis. A helically nonstraight blade lies flat on the floor face and has a front cutting edge lying radially outside the surface and a rear side confronting and spaced from the rear face of the seat. Blade bolts extending generally radially of the axis through the blade are seated in the body and secure the blade to the floor face with a possibility, when the blade bolts are not tightened, of limited movement of the blade on the floor face. A plurality of axially spaced spacer blocks each have a rear edge bearing against the rear face of the seat and a front edge bearing against the rear side of the blade.

Abstract: Fast loading of a vector test pattern in a semiconductor device tester. Fast loading is achieved through the use of delta coding of vectors in conjunction with a vector cache in the vector loading circuitry of the tester. In this way, the total amount of information transmitted during the loading operation is reduced. Hardware required to implement the method is minimized by using random access memory conventionally found in automatic test equipment for the vector cache.

Abstract: The invention relates to a sway brace on rail vehicles. The aim of the invention is to find a solution in which the effort and expense needed to produce the sprung sway braces can be reduced and the transverse forces and the resultant wear occurring on deflection can be reduced to the minimum. This is achieved by the invention in that one end of the sprung sway braces in a special design is arranged in a support with defined guide surfaces while the other end is secured to the piston of a hydraulic cylinder via an axial rocker beating. In addition, there is a disc spring column above the sway brace.

Abstract: Apparatus and method for detecting timing hazards which might be introduced in a pattern for execution on a tester when edges are improperly programmed in the pattern. The apparatus includes hazard detection circuits associated with the pins of the tester. Each circuit receives control inputs which specify which edges are involved in the hazard and limits on the permissible time between the specified edges. In operation, the pattern is executed repeatedly, once for each hazard which must be detected. The programmed times for the selected edge as well as the drive and format for each period of the pattern are variable inputs to the circuit.

Abstract: Automatic test equipment with a programmable timing generator. In the timing generator, the required delay is split into a course delay, a frequency adjustment delay, and a fine delay. The fine delays for successive cycles are temporarily stored. As the course delays pass, the fine delays are retrieved and used to generate edge signals. The frequency adjustment delay is used to offset the time at which the fine delay is retrieved by a fraction of a the resolution of the course delay. This arrangement allows the fine delay values to be retrieved at a higher rate than the rate at which the signals representing the required delays were generated. With this arrangement, the edges can be generated in a high frequency burst mode even though much of the timing generator is implemented with circuitry that has a lower operating frequency. A significant cost savings results by providing high frequency operation with less expensive components of lower operating frequency.

Abstract: A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit having a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.

Abstract: A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit has a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.

Abstract: An apparatus for processing failure information received from a node of a circuit under test. The apparatus includes a fail processor which receives test data from a node and generates failure data based upon the test data, a plurality of fail memories, each memory being configured to receive and store certain fail data, and a sequence memory configured-to store sequence information indicating in what order the failure data is stored in the plurality of fail memories.

Abstract: "The present invention provides an interpolator circuit including a register, a pulse swallower, a ramping circuit and a compare circuit. The interpolator may be employed in a high speed timing generator".