Abstract: The hybrid adder of the present invention uses stages of carry select functions to provide serial carries and a carry look-ahead tree structure to compute the final carries in parallel. The longer the carry select stages become, the slower and smaller the hybrid adder gets by reducing the size of the carry tree. By making the carry select stages shorter, the faster and larger the adder gets by increasing the size of the carry tree. The increased flexibility of the resulting hybrid adder gives the circuit designer a greater range of possible designs to achieve optimum size and speed performance. A preferred process for selecting optimum stage lengths is also described. The method for designing the hybrid adder is preferably carried out using a logic synthesis software program.

Abstract: Sequential encoding of Reed-Solomon codes using a discrete time delay line, a single adder, and a single multiplier provides efficient encoding of Reed-Solomon codes with or without interleaving. The encoder utilizes a clock whose rate is r times the symbol rate where r is the redundancy of the code. The finite field operations are performed in a sequential manner requiring only one finite field multiplier and one finite field adder. All memory elements are consolidated into a discrete time delay line which can be implemented with a random access memory. The encoder can be easily reconfigured for changes in generator polynomial of the code, the amount of redundancy, and interleaving depth.

Abstract: A structure and a method are provided for fast-decoding a Huffman code using means for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, and means for removing from the Huffman codeword the number of leading 1's recognized. In one embodiment, both JPEG Huffman code AC and DC tables are stored in a random access memory (RAM). In that embodiment, to access the AC code tables, an address is formed by the number of leading 1's recognized and the portion of Huffman code with the number of leading 1's recognized removed. To access the DC code tables, an address is formed by a predetermined code pattern and the Huffman codeword.

Abstract: A method and a structure are provided for decoding Huffman codes using a random access memory having a size less than twice the total number of codewords decodable. Under this method, the number of leading 1's in a Huffman codeword and the bits of the Huftman code word other than the leading 1's ("remainder") are combined to form an address into the random access memory. Using the fact that, for a given number of leading 1's in a Huffman code, the possible remainder of the Huffman code is no longer than a predetermined number of bits, the size of the random access memory necessary for decoding such Huffman codes can be made optimally small.

Abstract: A structure and a method are provided for fast-decoding a Huffman code using a leading 1's detector for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, so as to provide a class number in accordance with the number of leading 1's recognized, a first logic circuit for providing a "remainder" by removing from the Huffman codeword a number of bits in accordance with the class number, and a second logic circuit for recognizing a special class. In one embodiment, decoding is accomplished by accessing a storage device using an address formed by a table number, a subclass number derived from the class number and all of the bits in the remainder except the least significant bit.

Abstract: Apparatus for an array of digital signal processors that can be reconfigured as a one-dimensional or as a two-dimensional array; and method and apparatus for compensating for inconsistent time delays in signals processed by n-dimensional arrays of signal processors.