Abstract: A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value, initializing the resistivity changing memory cell into one of at least four resistivity changing memory states, detecting a second resistance value of the resistivity changing memory cell, determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value, and determining the state of the resistivity changing memory cell state using the first and the second result values.

Abstract: An integrated circuit includes an array of memory cells, and an error correction code circuit configured to correct errors in data read from the array based at least in part on a map that identifies locations of erratic memory cells in the array.

Abstract: An integrated circuit includes an array of resistivity changing memory cells. The integrated circuit includes a circuit configured to invert a data word to be written to the array in response to determining that writing the inverted data word would use less power than writing the non-inverted data word.

Abstract: The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

Abstract: Data transfer is effected on an internal and/or on an external transfer path with or in a semiconductor component, such as a semiconductor memory. A first multiplexer/demultiplexer codes a data sequence by defining a current level and a voltage level for a data signal. The coded sequence is then transferred on the transfer path synchronously with a clock signal and is decoded in a second multiplexer/demultiplexer by evaluation of the received current level and of the received voltage level. From this, the transferred data sequence is determined.

Abstract: The invention relates to a procedure for operating a bus system, as well as a bus system with a line, and two adjoining lines, whereby the lines each comprise two line sections, which are connected with one another by means of a line amplifier and/or buffer device, and whereby the line amplifier and/or buffer device connected with the line sections of the line is constructed as an inverting line amplifier and/or buffer device, and the line amplifier and/or buffer devices connected with the line sections of the adjoining lines are constructed as non-inverting line amplifier and/or buffer devices, or vice versa.

Abstract: An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

Abstract: An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

Abstract: A Method for initializing an asynchronous latch chain is described, wherein data are taken over through a latch stage at the beginning of the latch chain upon a request signal, the method comprising starting of a clock creation means, like for example a DLL (DLL=delay locket loop), for creating an internal clock on the basis of an external clock, resetting the asynchronous latch chain and applying a start signal to a request signal generation circuit whereupon the creation of a first request signal is enabled on the basis of the internal clock after the clock creation means is settled and after the asynchronous latch chain is reset.

Abstract: The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Abstract: Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

Abstract: In a method for reducing interferences in a voice signal, a noise reduction method is applied to the voice signal, and spectral psychoacoustic masking is taken into account. A spectral masking curve is determined both for the input signal and the output signal of the noise reduction method. By comparing the signal portions exceeding the respective masking curve, newly-audible portions are detected in the form of interference in the output signal and subsequently damped selectively.

Abstract: Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which [lacuna] a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

Abstract: The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

Abstract: An integrated circuit contains a register circuit for storing reference data for a test operation of the integrated circuit and a comparison circuit for comparing data to be read out. The comparison circuit outputs a plurality of comparison signals representing compressed comparison results. A plurality of output circuits are connected to the output of the comparison circuit, the output circuits receive one of the comparison signals in each case. The comparison signals are present at the output circuit over a plurality of clock edges or clock periods of a control clock. Each of the output circuits is connected to an interface pad for externally outputting the comparison signals. In the test operation, an external test device is connected to the interface pads of the integrated circuit. Despite a reduction in the transmission frequency to the test device, the full information content of the comparison signals can be transmitted.

Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Abstract: The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.