Patents by Inventor Peter Sean Feeley
Peter Sean Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11829290Abstract: A processing device in a memory system determines a rate at which an amount of valid data is decreasing on a first block of the memory device and determines whether the rate at which the amount of valid data is decreasing on the first block satisfies a threshold criterion. Responsive to the rate at which the amount of valid data is decreasing on the first block satisfying the threshold criterion, the processing device performs a media management operation on the first block of the memory device.Type: GrantFiled: December 23, 2020Date of Patent: November 28, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Sampath K. Ratnam, Ashutosh Malshe, Peter Sean Feeley
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Patent number: 11755472Abstract: A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.Type: GrantFiled: July 14, 2021Date of Patent: September 12, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale
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Patent number: 11709633Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.Type: GrantFiled: March 2, 2022Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, Jr., Kishore Kumar Muchherla, Sampath Ratnam
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Patent number: 11670381Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.Type: GrantFiled: May 6, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
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Patent number: 11626162Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.Type: GrantFiled: January 16, 2020Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventors: Koji Sakui, Akira Goda, Peter Sean Feeley
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Patent number: 11610632Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: GrantFiled: May 26, 2021Date of Patent: March 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
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Patent number: 11403228Abstract: Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).Type: GrantFiled: August 20, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Kulachet Tanpairoj, Jianmin Huang, Tomoko Ogura Iwasaki, Kishore Kumar Muchherla, Peter Sean Feeley
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Publication number: 20220188040Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.Type: ApplicationFiled: March 2, 2022Publication date: June 16, 2022Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, JR., Kishore Kumar Muchherla, Sampath Ratnam
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Patent number: 11355166Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.Type: GrantFiled: February 15, 2021Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventors: Koji Sakui, Peter Sean Feeley
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Patent number: 11269553Abstract: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.Type: GrantFiled: May 19, 2020Date of Patent: March 8, 2022Assignee: Micron Technology, Inc.Inventors: Gianni Stephen Alsasua, Harish Reddy Singidi, Peter Sean Feeley, Ashutosh Malshe, Renato Padilla, Jr., Kishore Kumar Muchherla, Sampath Ratnam
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Patent number: 11231982Abstract: A processing device in a memory system incrementally adjusts a center read voltage for a first block of a memory device by a first offset amount to generate an adjusted read voltage and causes the adjusted read voltage to be applied to the first block to determine an adjusted bit count associated with the adjusted read voltage. The processing device further determines whether a difference between the adjusted bit count and a previous bit count associated with a previous read voltage satisfies a first threshold criterion pertaining to an error threshold, and responsive to the difference between the adjusted bit count and the previous bit count not satisfying the first threshold criterion, determines a read window for the first block based on the previous read voltage.Type: GrantFiled: January 28, 2021Date of Patent: January 25, 2022Assignee: Micron Technology, Inc.Inventors: Jung Sheng Hoei, Peter Sean Feeley, Sampath K. Ratnam, Sead Zildzic, Kishore Kumar Muchherla
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Publication number: 20210342262Abstract: A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale
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Publication number: 20210287748Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: ApplicationFiled: May 26, 2021Publication date: September 16, 2021Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
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Patent number: 11106577Abstract: An amount of valid data for each data block of multiple data blocks stored at a first memory is determined. An operation to write valid data of a particular data block from the first memory to a second memory is performed based on the amount of valid data for each data block. A determination is made that a threshold condition associated with when valid data of the data blocks was written to the first memory has been satisfied. In response to determining that the threshold condition has been satisfied, the operation to write valid data of the data blocks from the first memory to the second memory is performed based on when the valid data was written to the first memory.Type: GrantFiled: October 30, 2018Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Sampath K. Ratnam, Ashutosh Malshe, Christopher S. Hale
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Publication number: 20210257008Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.Type: ApplicationFiled: February 15, 2021Publication date: August 19, 2021Inventors: Koji Sakui, Peter Sean Feeley
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Publication number: 20210257031Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.Type: ApplicationFiled: May 6, 2021Publication date: August 19, 2021Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
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Publication number: 20210255960Abstract: Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).Type: ApplicationFiled: August 20, 2020Publication date: August 19, 2021Inventors: Kulachet Tanpairoj, Jianmin Huang, Tomoko Ogura Iwasaki, Kishore Kumar Muchherla, Peter Sean Feeley
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Patent number: 11075163Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.Type: GrantFiled: July 27, 2015Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Koji Sakui, Peter Sean Feeley, Akira Goda
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Patent number: 11068197Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: July 2, 2019Date of Patent: July 20, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Ashutosh Malshe, Sampath Ratnam, Harish Reddy Singidi, Vamsi Pavan Rayaprolu
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Patent number: 11056156Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: January 22, 2020Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley