Abstract: A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide.

Abstract: A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide.

Abstract: A method for reducing polymer deposition on vertical surfaces of metal lines etched from a metallization layer disposed above a substrate. The method includes forming a hard mask layer above the metallization layer and providing a photoresist mask above the hard mask layer. The method further includes employing the photoresist mask to form a hard mask from the hard mask layer. The hard mask has patterns therein configured to form the metal lines in a subsequent plasma-enhanced metallization etch. There is also included removing the photoresist mask. Additionally, there is included performing the plasma-enhanced metallization etch employing the hard mask and an etchant source gas that includes Cl2 and at least one passivation-forming chemical, wherein the plasma-enhanced metallization etch is performed without employing photoresist to reduce the polymer deposition during the plasma-enhanced metallization etch.

Abstract: A method for forming a semiconductor device includes providing a semiconductor body having source and drain regions therein and a gate electrode on a portion of a surface of such body between the source and drain regions. A dielectric layer is provided on the surface of the semiconductor body over the source and drain regions. A dielectric material is formed over the dielectric layer and over the gate electrode. An inorganic, dielectric layer is formed over the semiconductor body dielectric material. The inorganic, dielectric layer is patterned into a mask to expose selected portions of the dielectric material, such portions being over the source and drain regions. An etch is brought into contact with the mask. The etch removes the exposed underlying portions of the dielectric material and exposed underling portions of the dielectric layer to thereby expose the portions of the source and drain regions.