Abstract: A data tag containing self-descriptive data, a method for reading such a data tag and a system for interpreting such a data tag are disclosed. Characterizing information about a first data element stored in a memory of the data tag is stored in a first header preceding a first data element. In addition, characterizing information about a second data element stored in the memory of the data tag is stored in a second header preceding a second data element. The application of a multitude of descriptive headers, each characterizing a data element stored in the data tag memory, facilitates flexible data storage on such devices. Furthermore, it also facilitates data compression due to the fact that field lengths can be characterized as well, thus excluding the presence of redundant bits in the data stored in the memory.

Abstract: Link startup systems, methods and devices associated with interconnects are described. Asymmetric lane connections are supported by, for example, independent renumbering of the connected lanes after an initial discovery process. Low-power, hibernating states of devices are supported by, for example, initialing alternating between transmission of startup and wakeup sequences over the interconnect between devices.

Abstract: Disclosed are methods, and control devices (110, 210, 310) having programmable processors configured to implement methods, of communicating with a network (100, 300) having an initially unknown topology and a plurality of unknown devices. The methods use set and get configuration commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

Abstract: A method of communicating between a transmitter and a receiver based on frames is provided. An error detection code is added to each frame to be transmitted by the transmitter. The frames to be transmitted by the transmitter are transmitted and the transmitted frames are received by the receiver. An error detection code is re-computed based on the received frames by the receiver. At least one frame which has been correctly received based on a comparison of the error detection code of each frame with the re-computed error detection code of each received frame is acknowledged. An error indication frame is sent by the receiver when an error is detected based on the comparison result. If a retransmission condition is detected by the transmitter by receiving an error indication frame from the receiver or if no acknowledgement frame was received by the transmitter from the receiver in a predetermined time interval, the currently transmitted frame is aborted and the transmitter inserts a trailer.

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.

Abstract: The establishment of reliable communication, in particular in an environment of the mobile industry processor interface where communication is taking place based on the Unified Protocol is described. In this case based on the timer at the sender and based on maintaining an originator of a message at the receiver certain precautions are taken that messages are exchanged correctly and only once an acknowledgement is received from the sender, that a first and a second message have been exchanged correctly a maintained originator at the receiver is released. The same method can also be applied to sending a plurality of messages in sequence by using sequence numbers and replying to them in the same manner. In this case the timer is always restarted, once the message as a first type of message is sent from the sender side and an acknowledgement is sent after the last second type of message with a highest sequence number has been received from the receiver side.

Abstract: A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

Abstract: Link startup systems, methods and devices associated with interconnects are described. Asymmetric lane connections are supported by, for example, independent renumbering of the connected lanes after an initial discovery process. Low-power, hibernating states of devices are supported by, for example, initialing alternating between transmission of startup and wakeup sequences over the interconnect between devices.

Abstract: Disclosed are methods, and control devices (110, 210, 310) having programmable processors configured to implement methods, of communicating with a network (100, 300) having an initially unknown commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

Abstract: A method of communicating between a transmitter and a receiver based on frames is provided. An error detection code is added to each frame to be transmitted by the transmitter. The frames to be transmitted by the transmitter are transmitted and the transmitted frames are received by the receiver. An error detection code is re-computed based on the received frames by the receiver. At least one frame which has been correctly received based on a comparison of the error detection code of each frame with the re-computed error detection code of each received frame is acknowledged. An error indication frame is sent by the receiver when an error is detected based on the comparison result. If a retransmission condition is detected by the transmitter by receiving an error indication frame from the receiver or if no acknowledgement frame was received by the transmitter from the receiver in a predetermined time interval, the currently transmitted frame is aborted and the transmitter inserts a trailer.

Abstract: A bus station circuit (14) operates in an electronic system with a bus (10). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

Abstract: A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (ST1-ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (ST1-ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (ST1-ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (ST1-ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts.

Abstract: A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state.

Abstract: A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

Abstract: A bus station circuit (14) operates in an electronic system with a bus (10). The bus station determines an initial synchronization time point by detecting a synchronization signal pattern on the bus and switching to a synchronization enabled state upon detection of the synchronization signal pattern. Starting points of successive messages are determined head to tail from the end points of immediately preceding messages, when operating in the synchronization enabled state. The content of the messages is tested for validity. The bus station switches to a synchronization disabled state in response to detection of a message with invalid content. While in the synchronization disabled state, use of messages that are received is disabled in the bus station circuit. In the synchronization disabled state the bus station waits for a synchronization event to switch back to the synchronization enabled state.

Abstract: An electronic device is provided with a plurality of functional units (1-10) for communicating at least primary and secondary data (ISOC; BE) based on frames (FR) each being divided into a number of time slot (SL), at least one network node (S1-S4) for coupling functional units (1-10) comprising at least one port (P1, P2, . . . , Pk) having an associated receiver port unit (RX1, RX2, . . . , RXk) for receiving at least primary and secondary data (ISOC; BE) from one of the plurality of functional units (1-10) in one of at least one first clock domain; and an associated transmitter port unit (TX1, TX2, . . . , TXk) for transmitting at least primary and secondary data (ISOC; BE) to another one of the plurality of functional units (1-10) in one of at least one second clock domain. The at least one second clock domain is different from the at least one first clock domain.

Abstract: A data tag containing self-descriptive data, a method for reading such a data tag and a system for interpreting such a data tag are disclosed. Characterizing information about a first data element (112) stored in a memory (310) of the data tag (300) is stored in a first header (110) preceding a first data element (112). In addition, characterizing information about a second data element (116) stored in the memory (310) of the data tag (300) is stored in a second header (114) preceding a second data element (318). The application of a multitude of descriptive headers, each characterizing a data element stored in the data tag memory (310), facilitates flexible data storage on such devices. Furthermore, it also facilitates data compression due to the fact that field lengths can be characterized as well, thus excluding the presence of redundant bits in the data stored in the memory (310).

Abstract: The invention describes the organizing and accessing of data pertaining to an engineering process. The process is partitioned into subprocess which are linked in a directed-acyclic-graph. Each link has a source node and a destination node, indicating which source node(s) must have been executed to provide the data necessary for executing the destination nodes. Executing any subprocess provides an instance of data associated to that node. The latter instances are linked in a second directed-acyclic-graph wherein each link indicates that part or all of the data at the source node has effectively been used for generating the data at its destination node. The two graphs are interlinked and provide for easy browsing of the data as well as for easy selection of input data for engineering subprocesses.