Abstract: This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.

Abstract: A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects.

Abstract: Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1(top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.

Abstract: A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower word line disturbance for a reliable DRAM-like latch sensing. A reduced precharge voltage can be increased by M-fold (M?2) using a Multiplier between each bitline and each Latch sense amplifier (SA). Between each Multiplier and each Latch SA, there is a Connector with two optional designs for either fully passing a sense voltage to the Latch SA with a same-polarity and value or reversing the polarity the sensing voltage with additional amplification. The Latch SA is configured to transfer stored threshold states of a memory cell into a bit of a page buffer.

Abstract: A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a stored ?Vt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM's power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that stored ?Vtp?1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification.

Abstract: This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.

Abstract: An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.

Abstract: A low-current FN channel scheme for erase, program, program-inhibit and read operations is disclosed for NAND NVM memories. This invention discloses a block array architecture and 3-step half-page program algorithm to achieve less error rate of NAND cell threshold voltage level. Thus, the error correction code capability requirement can be reduced, thus the program yield can be increased to reduce the overall NAND die cost at advanced nodes below 20 nm. As a result, this NAND array can still use the LV, compact PGM buffer for saving in the silicon area and power consumption. In addition, the simpler on-chip state-machine design can be achieved with the superior quality of less program errors.

Abstract: The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.

Abstract: This invention discloses 2D or 3D NAND flash array in two-level BL-hierarchical structure with flexible multi-page or random-page-based concurrent, mixed SLC and MLC Read, Program or Program-Verify operations including bit-flipping for each program state or any combinations of above operations. Tracking techniques of self-timed control and algorithm of programming, read and local-bit line (LBL) voltage generations are proposed for enhancing automatic controls over charging and discharging of a plurality of WLs and LBLs in one or more randomly selected Blocks in one or more Segments of one or more Groups in a NAND plane for m-page concurrent operations using Vdd/Vss to Vinh/Vss Program page data conversion, multiple pseudo CACHEs based on LBL capacitors for storing raw SLC and MSB/LSB loaded page data, writing back or reading from Sense-Amplifier, Program/Read Buffer, real CHCHE, and multiple pseudo CACHEs with M-fold reduction in latency and power consumption.

Abstract: A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I2C, SPI, SDI and SQI in one memory chip. The memory chip features write-while-write and read-while-write operations as well as read-while-transfer and write-while-transfer operations. The memory chip provides for eight pins of which two are for power and up to four pins have no connection for specific interfaces and uses a novel unified nonvolatile memory design that allow the integration together of the aforementioned memory types integrated together into the same semiconductor memory chip.

Abstract: A low-current FN channel for Erase, Program, Program-Inhibit and Read operations is disclosed for any non-volatile memory using FN-tunneling scheme for program and erase operation, regardless NAND, NOR, and EEPROM and regardless PMOS or NMOS non-volatile cell type. As a result, all above NMV memories can use the disclosed LV, compact PGM buffer to replace the traditional HV PGM buffer for saving in the silicon area and power consumption. The page buffer is used to store new loaded data for new writing and to convert the stored data into the required BL HV voltage for either Erase or Program operations according to the stored data. In addition, the simpler on-chip State-machine design can be achieved with the superior quality of NVMs of this disclosure.

Abstract: Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM's Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.

Abstract: This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based CAM logic cells connected in parallel sharing a local vertical SL and one dedicated vertical ML as an Operand word vertical page. Each 2T-string NOR-based CAM logic cell can be either a binary or ternary CAM cell associated with two or three physical states assigned to NAND cells' Vt levels for defining CAM logic states. Logic match of M-logic-bit inputs is found for at least one vertical page if the corresponding M 2T-string NOR-based CAM logic cells are in non-conduction state, providing M times faster Compare performance over the NAND-based CAM and 2 time faster than SRAM-based CAM.

Abstract: This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

Abstract: Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1(top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.

Abstract: An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment.

Abstract: The present invention discloses two preferred embodiments of a 12T NVSRAM cell with a flash-based Charger and a pseudo 10T NVSRAM cell with one shared Flash-based Charger. The Flash-based Charger can be made of a 2-poly floating-gate type or a 1-poly charge-trapping SONOS/MONOS flash type, regardless of PMOS type or NMOS type. In an alternative embodiment, the Store operation of above two preferred NVSRAM cell use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower associated with Flash Charger and 2-step SRAM amplification technique to amplify the threshold level difference ?Vt stored in the paired Flash transistors. The ?Vt can be detected as low as 1V when the coupled charges through the Flash charger are sufficient by ramping a gate control of the Flash Charger as high as VPP or by increasing the channel length for the Flash Charger.

Abstract: The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ?VQ-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM's VDD line and ramping down SRAM's VSS line.

Abstract: Several preferred embodiments of 1S1F 16T NVSRAM, 1S1F 20T NVSRAM, 1S2F 22T NVSRAM, 1S2F 14T NVSRAM cells are proposed, regardless of 1-poly, 2-poly, PMOS or NOS flash cell structures. Two separate sourcelines for the paired flash Strings are also proposed for easy adding ability for the NVSRAM circuit to detect the marginally erased Vt0 and marginally programmed Vt1 of the paired flash cell. By increasing an resistance added to common SRAM power line, the pull-down current through flash Strings to grounding source line can be made much larger than the pull-up current to improve SFwrite program operation. Simple method by increasing flash cell channel length to effectively enhance coupling area is applied to secure SRAM-to-Flash store operation under self-boost-program-inhibit scheme. 1S2F architecture also provide flexibility for alternate erasing and programming during both a recall and store operation.