Abstract: A communication system includes a destination node containing a message buffer pointer input queue and a message queue memory. Moreover, the message queue memory includes message buffers. A source node of the communication system generates data packets and a message buffer pointer packet. A message network of the communication system routes the data packets and the message buffer pointer packet to the destination node. The destination node writes a data message in a message buffer of the message queue memory based on the data packets and enqueues the message buffer pointer into the message buffer pointer input queue. Further, the destination node dequeues the message buffer pointer from the message buffer pointer input queue and accesses the data message in the message buffer based on a message buffer pointer.

Abstract: A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller performs a soft-decision inner error correction code decoding of the encoded data using a soft-decision algorithm and an outer error correction code decoding of the data decoded using the soft-decision inner error correction code decoding and then determining if the encoded data has been successfully decoded. If the encoded data has not been successfully decoded, the controller recovers the data by performing a RAID operation on the encoded data.

Abstract: A nonvolatile memory controller performs a data stripe operation on data blocks by processing a collection of commands. The nonvolatile memory controller includes command processing units, each of which processes a command of the data stripe operation to store a data block into a nonvolatile memory device. A parity calculator in the nonvolatile memory controller receives the data blocks of the data stripe operation by receiving a sequence of data blocks. The parity calculator generates a parity block in a page frame as the parity calculator receives the sequence of the data blocks. A command processing unit in the nonvolatile memory controller determines when the parity calculator has completed generating the parity block and writes the parity block to a nonvolatile memory device.

Abstract: A nonvolatile memory controller includes a host controller interface, processors, a message networks and a data network. The host controller interface includes a command fetch module, command assembly buffers, and a command dispatch module. The command fetch module retrieves nonvolatile memory commands from a host processing unit. The command assembly buffers store the nonvolatile memory commands retrieved from the host processing unit. The command dispatch module generates request message packets including the nonvolatile memory commands. The message network routes the request message packets to the processors. The processors process the nonvolatile memory commands in the request message packets for controlling operation of the nonvolatile memory controller.

Abstract: A nonvolatile memory controller processes a nonvolatile memory command and generates a completion status for the nonvolatile memory command. The nonvolatile memory controller transmits the completion status to a host processing unit for storage in a completion queue of the host processing unit. An interrupt manager in the nonvolatile memory controller determines the completion queue contains an unprocessed completion status and generates an interrupt message packet. The nonvolatile memory controller transmits the interrupt message packet to the host processing unit for triggering an interrupt in the host processing unit and alerting the host processing unit to the unprocessed completion status.

Abstract: A peripheral component interconnect express (PCIe) switch includes non-transparent endpoints, each of which is associated with a bus hierarchy domain. A source non-transparent endpoint in a source bus hierarchy domain receives a packet including a destination address and identifies a destination bus hierarchy domain including a destination non-transparent endpoint based on the destination address. Further, the source non-transparent endpoint translates a requester identifier in the packet to a translated requester identifier and generates a translated request packet including the translated requester identifier. The PCIe switch routes the translated request packet to the destination non-transparent endpoint through a non-transparent interconnect in the PCIe switch. In this way, the PCIe switch interconnects multiple bus hierarchy domains and is non-transparent in the multiple bus hierarchy domains.

Abstract: In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.

Abstract: A packet telephony appliance includes a Euphony network processor that integrates networking and DSP functions to provide a low cost and efficient solution in building a networked appliance. In particular, a Euphony ATM Telephone (EAT) is built around the Euphony network processor. The EAT uses a real-time operating system to provide predictable processing and networking support. The EAT implements IObufs, which provides a unified buffering scheme that allows zero-copy data movement. Furthermore, the EAT uses an Event Exchange (EVX), which provides a flexible mechanism for event distribution, allowing software modules to be composed together in an extensible manner. EVX and IObufs are used together to provide highly efficient intra-appliance communication. The EAT provides a platform that can evolve gracefully to support new protocols, advanced telephony services and enhanced user interfaces.

Abstract: A system and method for providing telephony and high-speed data access over a broadband access network, comprising a network interface unit (NIU) coupled to a backup local exchange carrier (LEC) line, the broadband access network coupled to the NIU, an intermediate point-of-presence (IPOP) coupled to the broadband access network, and at least one external access network coupled to the IPOP. The system also provides for a fail-safe mode in which the NIU supports the LEC line for lifeline services.

Abstract: A method and apparatus for generating a random bit stream in true random number generator fashion are described. Two periodic signals are employed in generating the random bit stream. A first periodic signal having preferably an approximately fifty percent duty cycle and jitter induced by supply and substrate noise is sampled by a second periodic signal that is relatively jitter-free and of a lower frequency than the first periodic signal.

Abstract: A packet telephony appliance includes a Euphony network processor that integrates networking and DSP functions to provide a low cost and efficient solution in building a networked appliance. In particular, a Euphony ATM Telephone (EAT) is built around the Euphony network processor. The EAT uses a real-time operating system to provide predictable processing and networking support. The EAT implements IObufs, which provides a unified buffering scheme that allows zero-copy data movement. Furthermore, the EAT uses an Event Exchange (EVX), which provides a flexible mechanism for event distribution, allowing software modules to be composed together in an extensible manner. EVX and IObufs are used together to provide highly efficient intra-appliance communication. The EAT provides a platform that can evolve gracefully to support new protocols, advanced telephony services and enhanced user interfaces.

Abstract: A DMA interrupt coalescer processes interrupts received from a DMA channel of a DMA controller by transmitting an interrupt request to an interrupt controller if a coalescing condition is satisfied after receiving one or more delayable interrupts, or transmitting the interrupt request regardless of the satisfaction of the coalescing condition if a non-delayable interrupt is received. The coalescing condition is satisfied if a non-zero period of time has transpired since a first of the one or more delayable interrupts was received, or if a number of the one or more delayable interrupts received exceeds a programmed value.

Abstract: A packet telephony appliance includes a Euphony network processor that integrates networking and DSP functions to provide a low cost and efficient solution in building a networked appliance. In particular, a Euphony ATM Telephone (EAT) is built around the Euphony network processor. The EAT uses a real-time operating system to provide predictable processing and networking support. The EAT implements IObufs, which provides a unified buffering scheme that allows zero-copy data movement. Furthermore, the EAT uses an Event Exchange (EVX), which provides a flexible mechanism for event distribution, allowing software modules to be composed together in an extensible manner. EVX and IObufs are used together to provide highly efficient intra-appliance communication. The EAT provides a platform that can evolve gracefully to support new protocols, advanced telephony services and enhanced user interfaces.

Abstract: A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU interface. Once written to, the protected area is only accessible to particular logic and cannot be over-written until the entire memory is erased. The controller is configured to allow a BCV to be stored in the memory through either the JTAG or CPU interface. The controller is also configured to allow writing to the protected area and boot configuration vector in memory before CPU boot-up by using a JTAG clock signal provided through an external pin when a system clock signal is not available. A reset circuit generates one or more initialization signals using either the BCV from memory or another BCV provided on external BCV pins, depending upon whether another external BCV pin is asserted.

Abstract: A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows for more. In a supplemental or alternate embodiment, at least one virtual bus is limited to having no devices on it. A non-transparent bridge is provided on at least one of the special buses for providing cross-border routing of packets from one root domain to another root domain. The number-of-devices limitation placed on the special bus reduces the number of bits needed in a corresponding Device identifying field of a destination ID Tag to 4 or less, this integer number being smaller than the prescribed 5 bits called for by the PCI-Express standard for addressing the maximum of 32 devices per bus.

Abstract: A reset circuit for resetting two clock domains resets the two clock domains synchronously with a first clock signal in response to assertion of a system reset. It then de-asserts the resetting of a first of the clock domains in synchronization with the first clock signal, and de-asserts the resetting of a second of the clock domains in synchronization with a second clock signal so that the second clock domain is not operative until after the second clock signal is running.

Abstract: A rate limiting circuit for data stream transmissions provides a generated clock signal to a buffer interposed between source and destination components so as to programmably adjust the maximum rate that data can be passed through the buffer. A counter is incremented by one each (1+RLmax) cycles of a clock signal, where RLmax is the larger of a user programmable value (RL) and a manufacturer one-time programmed value (SERL). A controller receiving a request to access the buffer for a read or write operation, checks the count of the counter before activating the access enable line. If the count is greater than zero, then the controller activates the access enable line while decrementing the counter by one. If the count is zero, however, then the controller waits until the count is greater than zero before activating the access enable line to grant the request.

Abstract: A packet telephony appliance includes a Euphony network processor that integrates networking and DSP functions to provide a low cost and efficient solution in building a networked appliance. In particular, a Euphony ATM Telephone (EAT) is built around the Euphony network processor. The EAT uses a real-time operating system to provide predictable processing and networking support. The EAT implements IObufs, which provides a unified buffering scheme that allows zero-copy data movement. Furthermore, the EAT uses an Event Exchange (EVX), which provides a flexible mechanism for event distribution, allowing software modules to be composed together in an extensible manner. EVX and IObufs are used together to provide highly efficient intra-appliance communication. The EAT provides a platform that can evolve gracefully to support new protocols, advanced telephony services and enhanced user interfaces.

Abstract: Method and device provide for the encapsulation of control information in a real-time data stream. In one embodiment a method of encapsulating data in an information frame is provided. This information frame has a payload portion and a trailer portion wherein the trailer portion is designated for control data and the payload portion is designated for real-time data. In use control data is inserted into the payload portion of the information frame and an extension bit is used to signify the presence of control data in the payload portion of the information frame. The information frame is then transmited over a virtual circuit.

Abstract: An event exchange mechanism for software systems is disclosed that utilizes a receiver-driven, publisher-subscriber model to overcome various problems in the prior art. The event exchange has a flexible addressing scheme so that a sending module need not be aware of all of its receiving modules. Yet, the event exchange still provides the ability to multicast messages to interested receivers. The system is also uniform since both data and control information can be exchanged using the same mechanism. Mechanisms for flow control are also provided so that a receiver can exert backpressure on a sender; this is especially useful for the transfer of multimedia data.