Abstract: A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.

Abstract: A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal.

Abstract: An arrangement for embedding supplemental data (e.g. a watermark W) in an information signal. In an embodiment of the invention, the arrangement comprises a conventional sigma-delta modulator for encoding an audio signal and modifying means for periodically replacing a bit of the encoded signal by a bit of the watermark. In the same manner, a sync pattern is embedded in the signal. The sync bits are embedded at a smaller distance than the watermark bits. Preferably, the sync pattern is a pattern of contiguous bits which is typically not generated by the encoder. For the sigma-delta modulator, such a pattern is a run of ones followed by a substantially equally long run of zeroes, or vice versa.

Abstract: Method of embedding watermarks in a signal encoded by an encoder having a feedback loop, for example, a sigma-delta modulator (21,22,23). A digital watermark pattern (w) is embedded in the signal (z) by modifying selected samples (for example, replacing every 100th bit) of the encoded signal (y) by samples of the watermark pattern. The circuit (24) for modifying the samples is located inside the loop of the encoder. The effect of watermarking is thus compensated in subsequent encoding steps and the signal-to-noise ratio is only slightly affected.

Abstract: A sigma-delta modulator comprising a low-pass filter of the Nth order, which is constituted by a series combination of N first-order integrating sections (6.1, 6.2, 6.3, . . . , 6.N) each comprising an integrator (12.1, 12.2, 12.3, . . . , 12. N) and a limiter (14.1, 14.2, 14.3, . . . , 14.N). The individual output signals of the sections are weighted by means of corresponding weighting amplifiers (16.1, 16.2, 16.3, . . . , 16.N) and the weighted signals are added together by an adder stage (18). The gains of the sections and the limit values of the limiters are selected so that the last limiter (14.N) in the series arrangement is activated first as the input signal level to the sigma-delta modulator increases, then the last-but-one limiter, and so on. This reduces the order of the filter system each time by one section as the input signal level increases above each successive limit value, thereby causing the sigma-delta modulator to remain stable at all signal levels.

Abstract: A gate circuit includes an N-channel and a P-channel insulated gate field-effect transistor whose parallel-connected drain-source paths constitute an analog signal gate and a control circuit, connected to the respective gate electrodes, to turn on and/or turn off the two field-effect transistors. In order to handle signals whose voltage value is higher than the maximum permissible drain-source voltage in the on-state of the N-channel field-effect transistor, means are provided, for turning on the N-channel field-effect transistor at least at a drain-source voltage below a predetermined value. In an embodiment of the invention the means include delay means coupled to the control circuit for turning on the N-channel field-effect transistor with a delay relative to the P-channel field-effect transistor. In another embodiment of the invention the means include switching means arranged in series with the analog signal gate, for temporarily connecting the signal gate to at least one auxiliary voltage.

Abstract: In a television signal memory write circuit which is synchronized by horizontal and vertical synchronizing signal patterns obtained from the television signal to be entered, the mutual positions of these patterns being measured with the aid of a measuring circuit; and depending on this measurement, the vertical synchronizing signal pattern is delayed by a variable delay circuit such that in practice the patterns are prevented from coinciding, thereby preventing a change in the position of a predetermined line number in the television signal memory circuit. This renders the circuit less sensitive to interference.