Abstract: With regard to a significant reduction in the tolerance range or margin to be taken into account in the design of a switched-capacitor circuit which is monolithically integrated by means of enhancement-mode insulated-gate field-effect transistors there is provided at least one opamp. This opamp contains a resistor which determines its quiescent current and is realized as a transistor operated in the permanently current-conducting state. An on-chip clock oscillator generates a clock signal. This oscillator is either an RC clock oscillator, whose frequency is determined by an oscillator resistor, which is realized as a transistor operated in the permanently current-conducting state, and an oscillator capacitor, or a current-controlled clock oscillator, whose frequency is determined by the quiescent current of the opamp. At least one capacitor is charged or discharged during operation by the opam via at least one switch in the form of a transistor clocked by the clock signal.

Abstract: This circuit arrangement has the property of an amplifier with a set or adjustable non-inverting gain and contains an opamp (3) having an a non-inverting and an inverting input (31, 32) as well as an output (33) which is also a signal output (A) of the circuit arrangement, and a current copier (8) having a current input and a current output. The noninverting input (31) is connected to a first reference potenial (P.sub.1) and the output (33) via a first resistor (1) to the inverting input (32). The input (E) of the circuit arangement is connected via a second resistor (2) to the current input of the current copier (8) the current output of which is connected to the inverting input (32). The output section of the current copier is connected to a second reference potential (P.sub.2) and its input section to the first reference potential.

Abstract: A circuit arrangement for the linearization and temperature compensation of capacitive sensor signals is provided which requires few components and wherein the compensated input signal is obtained fast. The arrangement includes: a clock generator; a reference capacitor; a measuring capacitor; a temperature-dependent voltage divider connected between an operating and a reference potential which measures the temperature of the measuring capacitor; an adjusting circuit which acts on the measuring capacitor and the reference capacitor and having a first input connected to the operating potential, a second input connected to the voltage divider, and a third input; an integrating stage connected to the measuring capacitor and the reference capacitor and having its output coupled to the third input of the adjusting circuit, the output being the output of the arrangement. The output signal is ##EQU1## where C.sub.v =(C.sub.m -C.sub.r)/C.sub.m, (C.sub.m -C.sub.r)/(C.sub.m +C.sub.r) , or (C.sub.m -C.sub.r)/C.sub.r ; C.

Abstract: A feed-back circuit for a high voltage generator including several voltage multiplying stages connected in series, wherein an oscillator generates two clock pulses being 180.degree. out of phase to one another, controlling alternately successive voltage multiplying stages to provide a high voltage pulse at the output of the high voltage generator, the high voltage output being connected to the feed-back circuit generating a control signal supplied to the oscillator, so that the two clock pulses are modified in dependence on the high voltage output voltage, wherein the feed-back circuit includes a high voltage feed-back circuit provided with a capacitive input stage (CP, CR), the output signal (VCTRLHV) of the high voltage feed-back circuit controlling the current of a controlled current source, and at least the oscillator generating the clock pulses receives the current as control signal and in dependence thereon controls the frequency of the clock pulses.

Abstract: Offset-compensated sample and hold arrangement to sample an input signal comprising at least an operational amplifier (A), a first capacitor (C1), a second capacitor (C2), a first switch (S110), a second switch (S211), a third switch (S210), a fourth switch (S111), a fifth switch (S120), a sixth switch (S121), a seventh switch (S220) and an eighth switch (S221), which switches capacitors and operational amplifier are interconnected in such a way and may be switched in such a way that during an offset-compensation phase the output voltage will only experience a very small voltage change.

Abstract: AC voltage clipper for a MOS-circuit having two input terminals (In1, In2) receiving an ac supply voltage, wherein one input terminal (In1) is connected to a point of common voltage through a first MOS-transistor (MCL41) and the other input terminal (In2) is connected to said point of common voltage through a second MOS-transistor (MCL42). The gates of MOS-transistors (MCL41, MCL42) are connected to each other and receive a gate voltage (Vg4) of a control circuit (MCL2, MCL3, DCL11,DCL12), in such a way that both transistors (MCL41, MCL42) will conduct when the absolute value of the ac supply voltage, being applied as an input signal to the control circuit (MCL2, MCL3, DCL11, DCL12) exceeds a predetermined threshold value.

Abstract: High voltage generator including several voltage multiplying stages connected in series, each having a diode and a capacitor one terminal of which being connected to the cathode of the respective diode, every cathode of a diode being connected to the anode of the diode of the next voltage multiplying stage, a clock generator generating two clock pulses being 180.degree. out of phase to one another and being supplied alternately to the other terminal of the capacitors of successive voltage multiplying stages, the last diode in the series supplying a high voltage output and the high voltage output being connected to feed-back circuit, modifying the two clock pulses in dependence on the voltage level on the high voltage output, at least the capacitor (Cn) in the last voltage multiplying stage receiving a control current (I1) determined by the feed-back circuit instead of one of both clock pulses.

Abstract: Biasing circuit for a class-AB Miller CMOS operational amplifier generating a first biasing voltage (VB1) for a MOS transistor (M5) determining the current through an operational amplifier input stage (M1 . . . M5), as well as a second biasing voltage (VB1C) for a MOS-transistor (M8) determining the current in a source follower stage (M8, M9), among others comprising a series connection of a MOS transistor (MB1) connected as a diode and a current source (Iref), the junction point being connected to the inverting input of a biasing operational amplifier (A), the non-inverting input of which receives a signal from the junction point from a series connection of two MOS transistors (M8C, M9C) being proportional to the source follower stage (M8, M9). The output of the biasing operational amplifier (A) is connected to the gate electrode of MOS transistor (M8C).