Patents by Inventor Petrus Hubertus Magnee

Petrus Hubertus Magnee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070120254
    Abstract: An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3).
    Type: Application
    Filed: December 20, 2004
    Publication date: May 31, 2007
    Inventors: Godefridus Hurkx, Prabhat Agarwal, Abraham Balkenende, Petrus Hubertus Magnee, Melanie Wagemans, Erik Petrus Antonius Bakkers, Erwin Hijzen
  • Publication number: 20070111485
    Abstract: A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).
    Type: Application
    Filed: December 9, 2004
    Publication date: May 17, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Johannes Josephus Theodorus Donkers, Petrus Hubertus Magnee
  • Publication number: 20060148257
    Abstract: Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.
    Type: Application
    Filed: December 16, 2003
    Publication date: July 6, 2006
    Inventors: Petrus Hubertus Magnee, Johannes Josephus Donkers, Xiaoping Shi