Patents by Inventor Phat Truong
Phat Truong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8988967Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.Type: GrantFiled: August 13, 2012Date of Patent: March 24, 2015Assignee: Nanya Technology Corp.Inventors: Phat Truong, Tien Dinh Le
-
Patent number: 8861291Abstract: The invention provides a memory apparatus and a signal delay circuit thereof. The signal delay circuit provided by present disclosure includes an input inverter, a first inverter, a capacitor, a first transistor, a second inverter and output inverter. The input inverter receives an input signal and output a signal to the first inverter. The capacitor coupled to an output terminal of the first inverter. The second terminal of the first transistor coupled to the output terminal of the first inverter and the first terminal of the first transistor coupled to an operating voltage. An input terminal of the second inverter is coupled to the output terminal of the first inverter and an output terminal of the second inverter is coupled to the control terminal of the first transistor. The output inverter is used to generate a delayed output signal.Type: GrantFiled: December 12, 2012Date of Patent: October 14, 2014Assignee: Nanya Technology CorporationInventors: Amna Shawwa, Phat Truong
-
Publication number: 20140160873Abstract: The invention provides a memory apparatus and a signal delay circuit thereof. The signal delay circuit provided by present disclosure includes an input inverter, a first inverter, a capacitor, a first transistor, a second inverter and output inverter. The input inverter receives an input signal and output a signal to the first inverter. The capacitor coupled to an output terminal of the first inverter. The second terminal of the first transistor coupled to the output terminal of the first inverter and the first terminal of the first transistor coupled to an operating voltage. An input terminal of the second inverter is coupled to the output terminal of the first inverter and an output terminal of the second inverter is coupled to the control terminal of the first transistor. The output inverter is used to generate a delayed output signal.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Inventors: Amna Shawwa, Phat Truong
-
Patent number: 8369165Abstract: A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.Type: GrantFiled: February 17, 2011Date of Patent: February 5, 2013Assignee: Nanya Technology CorporationInventors: Nhon Nguyen, Phat Truong, John Phan
-
Publication number: 20120307570Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Inventors: Phat TRUONG, Tien Dinh LE
-
Patent number: 8264907Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.Type: GrantFiled: October 14, 2009Date of Patent: September 11, 2012Assignee: Nanya Technology Corp.Inventors: Phat Truong, Tien Dinh Le
-
Publication number: 20120212273Abstract: A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Nhon Nguyen, Phat Truong, John Phan
-
Patent number: 8098083Abstract: A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage.Type: GrantFiled: April 2, 2009Date of Patent: January 17, 2012Assignee: Nanya Technology Corp.Inventors: Phat Truong, Mosaddiq Saifuddin, Chia-Jen Chang
-
Publication number: 20110176376Abstract: A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver.Type: ApplicationFiled: March 28, 2011Publication date: July 21, 2011Inventors: Chia-Jen Chang, Phat Truong
-
Patent number: 7940543Abstract: A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.Type: GrantFiled: March 19, 2008Date of Patent: May 10, 2011Assignee: Nanya Technology Corp.Inventors: Chia-Jen Chang, Phat Truong
-
Publication number: 20110085392Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.Type: ApplicationFiled: October 14, 2009Publication date: April 14, 2011Applicant: NANYA TECHNOLOGY CORP.Inventors: Phat TRUONG, Tien Dinh LE
-
Patent number: 7911262Abstract: An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.Type: GrantFiled: March 29, 2009Date of Patent: March 22, 2011Assignee: Nanya Technology Corp.Inventors: Phat Truong, Pauline Mai, Chia-Jen Chang
-
Patent number: 7834683Abstract: Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.Type: GrantFiled: May 30, 2008Date of Patent: November 16, 2010Assignee: Nanya Technology Corp.Inventors: Phat Truong, Jon Nguyen
-
Publication number: 20100253391Abstract: A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage.Type: ApplicationFiled: April 2, 2009Publication date: October 7, 2010Inventors: Phat Truong, Mosaddiq Saifuddin, Chia-Jen Chang
-
Publication number: 20100244940Abstract: An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.Type: ApplicationFiled: March 29, 2009Publication date: September 30, 2010Inventors: Phat Truong, Pauline Mai, Chia-Jen Chang
-
Patent number: 7737728Abstract: An off-chip driver (OCD) includes: a logic circuit, for providing a logic signal input; a pre-driver stage, coupled to the logic circuit, for providing a ramped up voltage in response to the logic signal input; a final driver stage, coupled to the pre-driver stage, for providing an output voltage in response to the ramped up voltage; and a bias circuit, coupled to the pre-driver stage, for providing a constant bias voltage to the pre-driver stage, wherein the constant bias voltage keeps the pre-driver stage within an operational range to compensate for variations in process, temperature and supply voltage.Type: GrantFiled: March 30, 2009Date of Patent: June 15, 2010Assignee: Nanya Technology Corp.Inventors: Phat Truong, Pauline Mai
-
Publication number: 20090295466Abstract: Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Phat Truong, Jon Nguyen
-
Publication number: 20090238014Abstract: A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Inventors: Chia-Jen Chang, Phat Truong
-
Publication number: 20070226553Abstract: Methods and apparatus that may be used to increase back-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the compression that may be achieved in back-end testing, particularly when only an indication of whether a device has passed or failed is required and no indication of a particular location of a failure is necessary.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Inventors: Khaled Fekih-Romdhane, Phat Truong
-
Patent number: 4820941Abstract: A driver circuit for applying both read and program voltages to a wordline of an integrated-circuit memory-cell logic array. The driver circuit is comprised of a series driver transistor pair, of a driver enabling means for enabling and disenabling one of the transistors of the driver transistor pair, and of a latching means. The driver transistor used during read operation may be constructed with a relatively short source-drain channel, permitting faster access speed during read operation of the circuit.Type: GrantFiled: February 1, 1988Date of Patent: April 11, 1989Assignee: Texas Instruments IncorporatedInventors: Debra J. Dolby, John F. Schreck, Phat Truong