Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: A built-in stress circuit for an integrated circuit that has a frequency generator, at least one self-test circuit, a temperature regulator and a controller is disclosed. The frequency generator receives a reference clock and an adjusted temperature frequency from the temperature regulator and outputs the test frequencies needed for the self-test circuits. The self-test circuits, which are coupled to the frequency generator, receive the test frequencies and dissipate power as the self-test circuits are being used. The temperature regulator, which is coupled to the self-test circuits and the frequency generator, senses the power dissipated (i.e., the temperature), adjusts a temperature frequency corresponding to the temperature desired, and outputs the adjusted temperature frequency. The controller, which is coupled to the frequency generator, the self-test circuits, and the temperature regulator, provides the control data necessary for testing both electrical and thermal stress conditions.

Abstract: The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.

Abstract: The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.