Abstract: The present invention provides a method and a computer system that compares a portion of a signal and information transferred from a cache memory, while the information is in transit from the cache memory. The information may be routed differently depending on the outcome of the compare. Specifically, the information may be delivered to a memory bus when it matches the portion of the signal and when the signal is a read command. Alternatively, the information may not be delivered to a memory bus when it matches the portion of the signal and when the signal is a write command. If the information does not match the portion of the signal, it may be transferred to a main memory via a memory bus. The information may be compared to the portion of the signal for a first time interval, and the portion of the signal may be compared to the information for a second time interval.

Abstract: A memory system includes a data memory for storing data and applications software and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode so that the memory capacity of the associated cache status memory can be up to seventy five percent smaller than the data memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller.

Abstract: A programmable memory controller is described. The memory control signals and timings are defined by programmable means. A plurality of shift registers are loaded with programmed values at the start of a control sequence. The programmed values are synchronously shifted with the optimum value system clock to thereby generate a plurality of memory control signals. Each memory control signal is generated by a shift register. Depending on the mode of operation to be performed by the memory device, different programmed values are loaded into the plurality of shift registers at the start of a control sequence. The selection of which programmed value to be loaded into the plurality of shift registers is accomplished by a multiplexer device coupled with each shift register. The multiplexer device selects one input mode register containing programmed values. One input mode register exists for each mode of operation that can be performed by the memory device.

Abstract: A memory system includes a data memory and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode while a read-modify-write operation is performed on an associated cache status memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller. Programmable control logic generates supplemental address lines based on the maximum number of data memory modules, the size of an addressed data memory module and the number of cache status columns.

Abstract: A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.

Abstract: A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. Each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment provides a plurality of allow mode signals to the other control segment.

Abstract: A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. However, each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment comprises a plurality of synchronous countdown register timers.

Abstract: A dynamic memory refresh apparatus includes a programmable refresh interval generator that generates an interval for generating a refresh request signal. The refresh interval time is based on the manufacturer specified DRAM cycle time, the system clock period, and the number of memory segments on the memory board that are supported by the computer system. The refresh interval time substantially maximizes the time between refreshes of a particular DRAM module. The dynamic refresh apparatus also includes a memory segment pointer generator that generates a memory segment pointer. The memory segment pointer points to the next memory segment to be refreshed. The memory segment pointer is generated such that the memory segments are selected in a staggered manner. In addition, the dynamic memory refresh apparatus includes a refresh request generator that generates a refresh request signal for the memory segment pointed to by the memory segment pointer.

Abstract: A system and method for automatically detecting the presence and configuration (e.g., number of rows and columns) of a writable memory module. A first data pattern is written to a first memory location. One or more data patterns different from the first data pattern are written to a second and subsequent memory locations in a walking-one sequence. After each write to the second and subsequent memory locations the data pattern at the first memory location is read. The read data pattern is compared to the first data pattern to determine if the first data pattern has been overwritten. The first data pattern is overwritten when the number of memory locations has been exceeded.