Abstract: Data is reformatted in a memory external to the processing elements of a processing array, relieving the processing array of this task and allowing it to perform its data processing functions more efficiently. Data is transferred to or from the multi-channel memory in a wordstream format, with individual data words mapped into the proper memory channels and the proper addresses within each channel in a matrix format. The invention is applicable to two-dimensional reformatting for data transfers between an input/output port and the memory, and to one-dimensional reformatting for data transfers between the processing array and either the memory or the input/output port. Logic circuitry within each channel selects the proper data words for that channel from a wordstream, and the associated address for each selected word, according to the respective positions of the data words in the wordstream.

Abstract: A data processor intended for a single instruction, multiple data mode operation includes memory that is external to the processor array, and a controller that dynamically and selectably interconnects multiple edges of the processor array with the memory and with I/O ports. A separate controller module is provided for each memory channel, and interconnects with corresponding edge processing elements of the processor array. The controller modules for the different channels are independent of each other, as are the channel memories. In the case of a rectangular processor array, each channel memory can be implemented with only three memory stores that are interconnected with the four edges of the processing array and the I/O ports through the channel controller module, yet for most algorithms provide a throughput that is comparable to that resulting from the use of four memory stores.

Abstract: A system and technique for synchronizing data to instructions. The inventive system (10) includes a processor (12), a first memory (14) for providing instructions to the processor (12), a second memory (16) for providing data to the processor (12); and a logic circuit (18, 20), responsive to the second memory (16), for synchronizing the input of instructions from the first memory (14) to the processor (12) based on the rate of flow of data into the second memory (16). In a particular implementation, the second memory (16) is a first-in, first-out (FIFO) memory which provides output data at a first output terminal and an `almost empty` output signal at a second output terminal thereof. The logic circuit includes an OR gate (18) having a first input terminal connected to the second terminal of the FIFO memory, a second input terminal connected to a source (22) of a clock signal and an output terminal.

Abstract: A data synchronizer (10) for synchronizing data generated by a data source (16) at a first rate includes a first timer (22) for generating a first timing signal at the first rate. A first register (20) connected to the first timer (22) has an input connected to the data source (16). The first register (20) temporarily stores multi-bit data words from the date source (16). A second timer (26) generates a second timing signal at the second rate. A second register (24) connected to the second timer (26) has an input connected to an output of the first register (20). The second register (24) temporarily stores multi-bit data words from the first register (20). A synchronizer connected to the first and second timers (22, 26) generates a good data signal when the multi-bit data words from the first register (20) is available at an output of the second register (24).