Abstract: A probe mechanism detects failed software components in a running software system. The probe mechanism is based on requesting service, or a certain level of service, from a set of functions, modules and/or subsystems and checking the response to the request. The probe is directed towards a service rendered by a collection of software modules and functions which is termed a target. The probe will then label a target as either healthy or failed. The objective is to localize the failure only up to the level of a target, however, and achieve a high degree of efficiency and confidence in the process. Targets are chosen such that they represent a collection of functions that can be defined by a service level input/output (I/O) specification. Targets can be identified at different levels or layers in the software. The choice of a level is based on the granularity of fault detection that is desired, taken in consideration with the level at which recovery can be implemented.

Abstract: A branch history table (BHT) is substantially improved by dividing it into two parts: an active area, and a backup area. The active area contains entries for a small number of branches which the processor can encounter in the near future and the backup area contains all other branch entries. Means are provided to bring entries from the backup area into the active area ahead of when the processor will use those entries. When entries are no longer needed they are removed from the active area and put into the backup area if not already there. New entries for the near future are brought in, so that the active area, though small, will almost always contain the branch information needed by the processor.The small size of the active area allows it to be fast and to be optimally located in the processor layout. The backup area can be located outside the critical part of the layout and can therefore be made larger than would be practicable for a standard BHT.

Abstract: In a digital data processing system including an Instruction Unit, an Execute Unit, and a multilevel Processor Storage System including a cache memory, additional apparatus is included referred to as a Load Control Block Address Unit for implementing a load control block address instruction which permits prefetching of data from main memory into cache simultaneous with execution of a sequence of instructions in a linked list wherein information determining starting address of a next block in the linked list is stored at a location in the current block at a fixed offset from the beginning of the block.