Abstract: Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.

Abstract: A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.

Abstract: Methods and systems for improved detection and classification of defects of interest (DOI) on semiconductor wafers based on three-dimensional images are described herein. Three dimensional imaging of volumes of thick, layered structures enables accurate defect detection and estimation of defect location in three dimensions at high throughput. A series of images are acquired at a number of different wafer depths. A three dimensional image of a thick semiconductor structure is generated from the series of images. Defects are identified and classified based on an analysis of the three dimensional image of the thick semiconductor structure. In some examples, the three-dimensional image stack is visualized by contour plots or cross-sectional plots to identify a characteristic defect response. In some examples, the three-dimensional image is processed algorithmically to identify and classify defects. In another aspect, the location of a defect is estimated in three dimensions based on the three dimensional image.

Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

Abstract: A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) including one or more programmed surface defects. The three-dimensional calibration structure includes a planarized layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on the planarized layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. One or more air gaps are formed in the layer stack following deposition of the cap layer. The three-dimensional calibration structure includes one or more holes formed into at least one of the cap layer, the layer stack, or the planarized layer.

Abstract: A defect inspection system includes an inspection sub-system and a controller communicatively coupled to the detector. The inspection sub-system includes an illumination source configured to generate a beam of illumination, a set of illumination optics to direct the beam of illumination to a sample, and a detector configured to collect illumination emanating from the sample. The controller includes a memory device and one or more processors configured to execute program instructions. The controller is configured to determine one or more target patterns corresponding to one or more features on the sample, define one or more care areas on the sample based on the one or more target patterns and design data of the sample stored within the memory device of the controller, and identify one or more defects within the one or more care areas of the sample based on the illumination collected by the detector.

Abstract: Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.

Abstract: Methods and systems for improved detection and classification of defects of interest (DOI) on semiconductor wafers based on three-dimensional images are described herein. Three dimensional imaging of volumes of thick, layered structures enables accurate defect detection and estimation of defect location in three dimensions at high throughput. A series of images are acquired at a number of different wafer depths. A three dimensional image of a thick semiconductor structure is generated from the series of images. Defects are identified and classified based on an analysis of the three dimensional image of the thick semiconductor structure. In some examples, the three-dimensional image stack is visualized by contour plots or cross-sectional plots to identify a characteristic defect response. In some examples, the three-dimensional image is processed algorithmically to identify and classify defects. In another aspect, the location of a defect is estimated in three dimensions based on the three dimensional image.

Abstract: Reverse decoration can be used to detect defects in a device. The wafer can include NAND stacks or other devices. The defect can be a channel bridge, a void, or other types of defects. Reverse decoration can preserve a defect and/or can improve defect detection. A portion of a layer may be removed from a device. A layer also may be added to the device, such as on the defect, and some of the layer may be removed.

Abstract: A defect inspection system includes an inspection sub-system and a controller communicatively coupled to the detector. The inspection sub-system includes an illumination source configured to generate a beam of illumination, a set of illumination optics to direct the beam of illumination to a sample, and a detector configured to collect illumination emanating from the sample. The controller includes a memory device and one or more processors configured to execute program instructions. The controller is configured to determine one or more target patterns corresponding to one or more features on the sample, define one or more care areas on the sample based on the one or more target patterns and design data of the sample stored within the memory device of the controller, and identify one or more defects within the one or more care areas of the sample based on the illumination collected by the detector.

Abstract: An optical waveguide is provided which comprises a non-solid core layer surrounded by a solid-state material, and two light sources capable of introducing light into said non-solid core at opposite ends along a Z-axis of said non-solid core to form two propagating light beams applying force in opposing directions. An integrated optical particle trap device for controlling the placement of small sample particles incorporates the optical waveguide.

Abstract: An optical waveguide is provided which comprises a non-solid core layer surrounded by a solid-state material, and two light sources capable of introducing light into said non-solid core at opposite ends along a Z-axis of said non-solid core to form two propagating light beams applying force in opposing directions. An integrated optical particle trap device for controlling the placement of small sample particles incorporates the optical waveguide.