Abstract: A method of projected capacitance touch sensing on a display includes updating the display by applying a drive waveform to each pixel of the display over a plurality of frame periods to update a pixel state. The updating includes selecting each row of the display in turn and repeating a frame update to drive pixels with successive time slices of the drive waveforms. The method further includes sensing a signal from a projected capacitance touch sensing electrode of the display during a sensing interval to provide a touch sensing response; identifying when column drive levels of the drive waveforms for pixels of one selected row change by more than a threshold level between the selected row and a next selected row; and inhibiting the touch sensing responsive to the column drive row change signal indicating a greater than the threshold level change of the drive levels between the selected rows.

Abstract: A method updates an image displayed on an electronic display. The image can include a first region having multiple lines and a second region also having multiple lines. The method includes driving the pixels of the first and second regions according to one or more frames. In a first frame, driving the pixels of the first and second regions is done by scanning the lines of the regions from a first end of the first region to a second end of the second region, the second end opposite the first end along a scanning direction. In a second frame, driving the pixels of the first and second regions is done by scanning the lines of the regions from the first end to the second end, and the scanning begins before the scanning according to the first frame reaches the second end.

Abstract: A method of projected capacitance touch sensing on a display screen, the method comprising: updating said display screen by applying a drive waveform to each pixel of the display screen over a plurality of frame periods, wherein a said drive waveform for a pixel defines a transition of the pixel from a current pixel state to an updated pixel state over said plurality of frame periods, and wherein said updating comprises selecting each row of said display screen in turn for a row driving period and driving columns of the display screen with a time slice of drive waveforms for pixels of the row to perform a frame update of said display screen, and repeating said frame update to drive pixels of said display with a plurality of successive time slices of said drive waveforms to drive said pixels with said drive waveforms; sensing a signal from a projected capacitance touch sensing electrode of said display screen during a sensing interval, and using said sensing to provide a touch sensing response; identifying whe

Abstract: A method updates an image displayed on an electronic display. The image can include a first region having multiple lines and a second region also having multiple lines. The method includes driving the pixels of the first and second regions according to one or more frames. In a first frame, driving the pixels of the first and second regions is done by scanning the lines of the regions from a first end of the first region to a second end of the second region, the second end opposite the first end along a scanning direction. In a second frame, driving the pixels of the first and second regions is done by scanning the lines of the regions from the first end to the second end, and the scanning begins before the scanning according to the first frame reaches the second end.

Abstract: We describe a switch mode power supply (SMPS) controller employing a combination of pulse frequency and pulse width modulation. The controller employs a “gear box” control scheme using two complementary control loops, one for real-time control of the SMPS using PFM and a second using a PWM control scheme which monitors the switching frequency and, at defined operating points, adjusts the pulse width up or down through a set of pre-determined values. This can be considered analogous to the gearbox of a motor vehicle with the SMPS pulse width, switching frequency and output power roughly corresponding to the vehicle's gear ratio, engine speed and road speed respectively.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor.

Abstract: Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A data processing apparatus for rounding an input number coded in a redundant bit form including a magnitude signal and a sign signal for each bit of the input number. A carry path control signal generator (372, 382) forms carry/borrow control signals for each bit of the input number from the corresponding magnitude signal and sign signal. A first borrow ripple unit (386) receives the carry/borrow control signals corresponding to a set of the least significant bits of the input number and a "0" borrow in signal for its least significant and generates a normal coded data signal and a borrow out signal for a most significant bit of this set of least significant bits. A second borrow ripple unit (376) receives the carry/borrow control signals corresponding to the most significant bits and a "1" borrow in signal for its least significant bit and generates a first rounded number having a normal coded data signal.

Abstract: A data processing apparatus for rounding an input number coded in a redundant bit form including a magnitude signal and a sign signal for each bit of the input number. A carry path control signal generator (372, 382) forms carry/borrow control signals for each bit of the input number from the corresponding magnitude signal and sign signal. A first borrow ripple unit (386) receives the carry/borrow control signals corresponding to a set of the least significant bits of the input number and a "0" borrow in signal for its least significant and generates a normal coded data signal and a borrow out signal for a most significant bit of this set of least significant bits. A second borrow ripple unit (376) receives the carry/borrow control signals corresponding to the most significant bits and a "1" borrow in signal for its least significant bit and generates a first rounded number having a normal coded data signal.

Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235).

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235).

Abstract: Apparatus for detecting the leftmost "1" bit or the rightmost "1" bit of an input number includes a binary tree (11) of two-inputs OR-gates (13, 14, 15, 16) or their logical equivalent to which the input number is applied in parallel and from which signals are derived and applied as inputs and to control a plurality of trees (MA, MB, MC) of two-input multiplexers (12) from the outputs (E0, E1, E2, E3) of which appear the bits of a number representing the position in the input number of the leftmost "1" or the rightmost "1" bit.