Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

Abstract: Image rejection calibration includes initializing the calibration mode by applying to quadrature mixers, in place of the wanted RF input, an RF source in the frequency range of the wanted RF input, sensing the power output from the poly-phase filter, developing gain adjust and phase adjust correction values in response to the power output and adjusting in accordance with the correction values the gain of the quadrature signals from the quadrature mixers to the poly-phase filter and the phase of local oscillator quadrature signals from the local oscillator to the quadrature mixers to reduce the power output.

Abstract: Embodiments of a system for calibrating the image rejection of a receiver include an image-rejection correction circuit that modifies the gain and phase of a first channel of a baseband image signal. The image-rejection correction circuit may include a summing circuit and first and second variable-gain elements. In one implementation, a filter receives a corrected first channel from the image-rejection correction circuit and an unmodified second channel of the image signal, while a controller analyzes power measured at the output of the filter, and adjusts the variable-gain elements to reduce the power of the image signal.

Abstract: Embodiments of a system for calibrating the image rejection of a receiver include an image-rejection correction circuit that modifies the gain and phase of a first channel of a baseband image signal. The image-rejection correction circuit may include a summing circuit and first and second variable-gain elements. In one implementation, a filter receives a corrected first channel from the image-rejection correction circuit and an unmodified second channel of the image signal, while a controller analyzes power measured at the output of the filter, and adjusts the variable-gain elements to reduce the power of the image signal.

Abstract: Image rejection calibration includes initializing the calibration mode by applying to quadrature mixers, in place of the wanted RF input, an RF source in the frequency range of the wanted RF input, sensing the power output from the poly-phase filter, developing gain adjust and phase adjust correction values in response to the power output and adjusting in accordance with the correction values the gain of the quadrature signals from the quadrature mixers to the poly-phase filter and the phase of local oscillator quadrature signals from the local oscillator to the quadrature mixers to reduce the power output.

Abstract: A digital frequency measurement system including first and second digital differentiators responsive to first and second digital quadrature signals representative of first and second quadrature modulated input signals that represent binary data having a center frequency equal to a predetermined IF frequency for generating first and second differentiated signals, first and second processing circuits responsive to the first and second digital quadrature signals representative of the modulated input signals and the first and second differentiated signals for multiplying the first differentiated signal by the second quadrature digital representation of the input signals and multiplying the second differentiated signal by the first quadrature digital representation of the input signals to provide first and second multiplied signals, a combining circuit responsive to the first and second multiplied signals for generating a density signal having a pulse density proportional to the frequency of the input signals, a d

Abstract: An FSK demodulator system with tunable spectral shaping including a pair of quadri-correlators responsive to first and second quadrature signals, one of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at even integer multiples of the frequency deviation and for resolving the modulated FSK data represented by the quadrature signals and the other of the pair deriving first and second signals representative of the frequency deviation of the quadrature signals at odd integer multiples of the deviation frequency and for resolving the modulated FSK data represented by the quadrature signals, and a delay control circuit for setting a delay to each of the pair of quadri-correlators to control the first and second signals representative of the frequency deviation of the quadrature signals derived by each of the pair of quadri-correlators and generate a tuned spectral response at both even and odd integer multiples of the frequency deviation.

Abstract: The invention provides an apparatus for decoding a coded digital data sequence. The apparatus includes a first Viterbi decoder of a first response type, a first filter and a second filter. The first and second filters are coupled to receive decoded sequences from the first Viterbi decoder. The first Viterbi decoder generates a first decoded sequence from the coded digital data sequence. The first and second filters generate respective first and second error signals in response to receiving the first decoded sequence. The first and second error sequences indicate differences between the first decoded sequence and second and third decoded sequences, respectively. The second and third decoded sequences are probable sequences produced by Viterbi decoders of respective second and third response types in response to receiving the coded digital data sequence.

Abstract: A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

Abstract: A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a "one of" circuit driving a ROM encoder stage. The ROM constitutes a "one-of" to Gray- or modified Gray code encoder, or a "one-of" to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a V.sub.DD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source "on" resistance, R.sub.

Abstract: A differential string DAC is provided including a coarse DAC which includes a plurality of coarse resistors connected in series between first and second reference voltage leads. A positive sub-DAC includes a plurality of positive sub-DAC cells, each positive sub-DAC cell including a multitude of series-connected fine resistors. A negative sub-DAC includes a plurality of negative sub-DAC cells, each negative sub-DAC cell including a multitude of series-connected fine resistors. Each coarse resistor is electrically connected in parallel with one positive sub-DAC cell and one negative sub-DAC cell. The positive sub-DAC cell and negative sub-DAC cell are substantially symmetrically disposed about the corresponding coarse resistor. Due to the differential arrangement and symmetrical layout of the DAC, INL errors due to process gradients in one direction across the DAC are greatly reduced. Process gradients in a second orthogonal direction are not of great concern as they cause much smaller INL errors.

Abstract: A servo system for controlling the position of a read/write head in a disk drive is provided. The servo system includes an input terminal for sequentially receiving a plurality of input signal bursts of a burst pattern, wherein the input signal bursts include positional information of the head. Demodulation circuitry, coupled to the input terminal, sequentially demodulates each input signal burst and provides a demodulated signal for each burst. An ADC, coupled to the demodulation circuitry, sequentially converts each demodulated signal. The ADC converts a first demodulated signal corresponding to the first of the plurality of input signal bursts before the demodulation circuitry completes demodulating the next of the plurality of input signal bursts. In a preferred embodiment, the ADC converts a demodulated signal corresponding to a first input signal burst while the demodulation circuitry demodulates a signal corresponding to a second, and subsequent, input signal burst.