Patents by Inventor Philip Rutter
Philip Rutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
EDGE TERMINATION STRUCTURE FOR A CHARGE BALANCED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
Publication number: 20240154032Abstract: An enhanced edge termination structure for use in a charge balanced semiconductor device is provided. The edge termination structure includes a plurality of edge termination trenches and a plurality of semiconductor mesa regions, each of the mesa regions being disposed between adjacent edge termination trenches. The edge termination trenches extend outwardly from an active region of the device on at least two adjacent sides of the active region when viewed in a plan view. The edge termination trenches are orthogonal to a corresponding edge of the active region from which they extend.Type: ApplicationFiled: October 26, 2023Publication date: May 9, 2024Inventors: Philip Rutter, Stanislav Soloviev, David Jauregui -
Publication number: 20240145532Abstract: A semiconductor device is provided that includes an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in which at least one edge termination structure is formed, the edge termination region being laterally adjacent to the active region. The semiconductor device further includes a charged layer disposed on an upper surface of the epitaxial layer, the charged layer covering at least a portion of the active region and extending laterally over at least a portion of the edge termination region. Active trenches may be formed in the active region, and at least one edge trench may be formed in the edge termination region. The charged layer may be formed on sidewalls of each of the active trenches and the edge trench using atomic layer deposition in a same processing step.Type: ApplicationFiled: September 11, 2023Publication date: May 2, 2024Inventors: David Jauregui, Stanislav Soloviev, Philip Rutter
-
Patent number: 10153365Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.Type: GrantFiled: August 10, 2016Date of Patent: December 11, 2018Assignee: Nexperia B.V.Inventors: Steven Thomas Peake, Philip Rutter, Chris Rogers
-
Patent number: 9941265Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.Type: GrantFiled: July 1, 2016Date of Patent: April 10, 2018Assignee: Nexperia B.V.Inventors: Philip Rutter, Jan Sonsky, Barry Wynne, Yan Lai, Steven Thomas Peake
-
Publication number: 20180006015Abstract: Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: Philip Rutter, Jan Sonsky, Barry Wynne, Yan Lai, Steven Thomas Peake
-
Patent number: 9735254Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.Type: GrantFiled: March 11, 2015Date of Patent: August 15, 2017Assignee: Nexperia B.V.Inventors: Steven Thomas Peake, Philip Rutter
-
Patent number: 9608514Abstract: Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.Type: GrantFiled: February 3, 2015Date of Patent: March 28, 2017Assignee: NXP B.V.Inventors: Henricus Cornelis Johannes Buthker, Matthias Rose, Philip Rutter, Jan Sonsky
-
Publication number: 20170077291Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.Type: ApplicationFiled: August 10, 2016Publication date: March 16, 2017Inventors: Steven Thomas Peake, Philip Rutter, Chris Rogers
-
Patent number: 9472549Abstract: A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.Type: GrantFiled: October 17, 2013Date of Patent: October 18, 2016Assignee: NXP B.V.Inventors: Matthias Rose, Jan Sonsky, Philip Rutter
-
Patent number: 9268351Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.Type: GrantFiled: March 13, 2014Date of Patent: February 23, 2016Assignee: NXP B.V.Inventors: Philip Rutter, Maarten Swanenberg
-
Patent number: 9171837Abstract: A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.Type: GrantFiled: December 3, 2013Date of Patent: October 27, 2015Assignee: NXP B.V.Inventors: Philip Rutter, Jan Sonsky, Matthias Rose
-
Patent number: 9129991Abstract: A method to manufacture a vertical capacitor region that comprises a plurality of trenches, wherein the portions of the semiconductor region in between the trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.Type: GrantFiled: April 9, 2014Date of Patent: September 8, 2015Assignee: NXP B.V.Inventor: Philip Rutter
-
Publication number: 20150229205Abstract: Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.Type: ApplicationFiled: February 3, 2015Publication date: August 13, 2015Inventors: Henricus Cornelis Johannes Buthker, Matthias Rose, Philip Rutter, Jan Sonsky
-
Publication number: 20150187913Abstract: A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Steven Thomas Peake, Philip Rutter
-
Publication number: 20140292287Abstract: A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.Type: ApplicationFiled: March 13, 2014Publication date: October 2, 2014Applicant: NXP B.V.Inventors: Philip RUTTER, Maarten SWANENBERG
-
Publication number: 20140220749Abstract: Consistent with an example embodiment, a method of may be provided to manufacture a vertical capacitor region that comprises a plurality of said trenches, wherein the portions of the semiconductor region in between said trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.Type: ApplicationFiled: April 9, 2014Publication date: August 7, 2014Applicant: NXP B.V.Inventor: Philip RUTTER
-
Publication number: 20140167822Abstract: A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.Type: ApplicationFiled: December 3, 2013Publication date: June 19, 2014Applicant: NXP B.V.Inventors: Philip Rutter, Jan Sonsky, Matthias Rose
-
Publication number: 20140145208Abstract: A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.Type: ApplicationFiled: October 17, 2013Publication date: May 29, 2014Applicant: NXP B.V.Inventors: Matthias ROSE, Jan SONSKY, Philip RUTTER
-
Patent number: 8652904Abstract: A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.Type: GrantFiled: September 20, 2011Date of Patent: February 18, 2014Assignee: NXP, B.V.Inventors: Philip Rutter, Christopher Martin Rogers
-
Patent number: 8513733Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.Type: GrantFiled: August 15, 2011Date of Patent: August 20, 2013Assignee: NXP B.V.Inventors: Steven Thomas Peake, Philip Rutter