Abstract: A circular scan streak tube system for recording fast optical data includes a target having a first array of detection elements and a second array of corresponding storage elements. Changes in the scanning electron beam current representing optical events are detected and stored in the first array. The first and second arrays are segmented into two halves for continuous operation. Data stored in one half of the first array are transferred into the corresponding storage elements while data are written into the other half of the first array. Data stored in the first array are transferred in parallel to the second array. After a triggering event, the data are shifted circumferentially through the second array for output as serial data. The target is formed in a unitary planar semiconductor substrate having a buried channel for storing and conducting electric charge representing the stored data.

Abstract: A hierarchical current amplifier includes a first current mirror tier including a current mirror having an input coupled to an amplifier base terminal for receiving an input current, an output coupled to an amplifier collector terminal, and a pair of emitter terminals. A second current mirror tier includes two current mirrors corresponding to each emitter terminal in the first current mirror tier, each current mirror having an input coupled to one of the emitter terminals of the current mirror in the first current mirror tier. The two current outputs in the second tier are coupled to the amplifier collector terminal to provide current gain. Successive tiers of current mirrors may be added to provide more current gain.

Abstract: Jitter in a clock signal is measured by using the clock signal to clock a digitizer repetitively digitizing a highly stable sine wave signal so as to produce a first data sequence representing the magnitiude of the sine wave signal as a function of time. This first data sequence is normalized to produce a second data sequence having data elements that vary between maximum and minimun magnitudes of +1 and -1. The arcsine of each element of the second data sequence is then determined to provide a monotonically increasing third data sequence, wherein each element of the third data sequence indicates a phase angle associated with a corresponding element of the second data sequence. A fourth data sequence is then generated, each element of the fourth data sequence representing a difference between a phase angle represented by a corresponding element of the third data sequence and a phase angle that the corresponding element of the third data sequence would represent if the clock signal had a constant frequency.

Abstract: A method and apparatus for determining the effective bits of resolution of a digitizer wherein amplitude, frequency, phase angle and offset parameters characterizing a sinewave input signal to the digitizer are estimated from the waveform data sequence produced by the digitizer in response to the input signal. These estimated parameters are used to develop a model of the sinewave signal, and the effective bits of resolution of the digitizer are then determined by the comparing measured magnitudes of the sinewave signal as represented by the waveform data sequence to estimated magnitudes of the input signal being determined from the model.

Abstract: A signal generator for producing a triggered output signal of digitally controlled phase and frequency includes a skewing circuit for producing an output clock signal of the same period, T, as an input, triggered reference clock signal but which is phase skewed from the reference clock signal by a phase angle, P, of 0 to 360 degrees as determined by input digital data. The skewed clock signal is frequency divided by an integer factor N, and a timing circuit counts reference clock periods to initiate frequency division a programmable delay time (J.times.T seconds) following triggering of the reference clock signal, where J and N are integers also determined by input digital data. An AND gate qualifies the frequency divided skewed clock signal with the skewed clock signal itself to produce a periodic output signal of digitally controlled frequency N/T, the first pulse of which is delayed following triggering of the reference signal by a digitally controlled interval of (T.times.J)+(P.times.T/360) seconds.

Abstract: A testing method and apparatus employs electron beam writing and reading of conductive paths in a circuit device rather than physical probing of conductive elements. Portions of the circuit device, e.g., conductive paths, are bistably stored at a given potential and then the device is read by a reading beam to determine if proper connections exist. Read out is at comparatively high levels represented by the difference between bistable voltage values. Once a portion of the device has been tested, it may remain in stored condition such that additional cross checking or repetition of testing is rendered unnecessary.

Abstract: A digital dither generator is described which produces a series of discrete analog values which remain constant for each repetition of a signal being digitized. These analog values are summed with the analog input value being digitized. The dither states exhibit two useful characteristics; a bit-reversal scheme in which a sequence of dither values is used to progressively maximize the resolution of the digitizer and a technique of offsetting the values by a known amount to statistically improve digitizer accuracy.

Abstract: Two multiplying digital-to-analog converters are used to digitally weight an analog current to produce a controllable output current. The output current is selected by a digital control signal applied to the control inputs of both converters. Two-quadrant operation is ensured by feeding the analog output of each converter to a current mirror amplifier which develops the required output current.

Abstract: A second-order phase-locked loop circuit which does not require error voltage amplification is described. The output of a voltage controlled oscillator is accurately phase locked to a reference pulse. The loop phase detector is periodically enabled by a pulse generator and draws current only when enabled. Therefore very little noise may be coupled to the voltage controlled oscillator. The phase detector incorporates a current amplifier which allows very accurate establishment of the instant phase comparison takes place.