Abstract: A semiconductor process is disclosed which forms a field plate structure that integrally contacts an emitter region of a bipolar junction transistor by construction, without intervening interconnect layers or contacts. In one embodiment, a single-layer polysilicon electrode forms a field plate electrode which integrally interconnects to a traditional diffused emitter region formed before the polysilicon layer is deposited. This allows for deeper emitter regions required by the deep base regions needed for high-voltage bipolar devices. Moreover, the polysilicon layer, including the polysilicon electrode forming the field plate electrode, may be used as a local interconnect layer.

Abstract: A semiconductor process is disclosed which forms openings in a dielectric layer through which the base region of both high-voltage and high-gain bipolar transistors are formed. In one embodiment of the invention, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the openings for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques.

Abstract: A semiconductor fabrication process uses an epitaxial layer as an etch stop in a plasma etch process. In one embodiment, mechanical stops and an epitaxial layer are used in combination for stopping precisely at a desired end point.

Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.