Abstract: A digital decoder for use with a dual bus system is provided having a minimum number of transistors. The decoder is easily expandable to decode larger binary coded input signals. As a minimum only six transistors are needed to decode a three-bit binary input signal to provide outputs for a data bus and its complement. By using a minimum number of transistors, less current is required for the decoder. The circuitry used to provide each decoded output is repeated in a manner which conserves silicon area when the decoder is placed on silicon. A minimum number of control lines are used.

Abstract: A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register.

Abstract: An increment/decrement circuit is provided which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/decrement circuit and also uses a reduced number of transistors. The increment/decrement circuit has a carry/borrow generator and has an increment/decrement output portion. The carry/borrow generator uses only three transistors plus an inverter and two coupling transistors. The increment/decrement output portion uses only six transistors.