Abstract: A camera device includes monochromatic and color image sensors that capture an image as a clear image in monochrome and as a Bayer image. The camera device implements image processing algorithms to produce an enhanced, high-resolution HDR color image. The Bayer image is demosaiced to generate an initial color image, and a disparity map is generated to establish correspondence between pixels of the initial color image and clear image. A mapped color image is generated to map the initial color image onto the clear image. A denoised clear image is applied as a guide image of a guided filter that filters the mapped color image to generate a filtered color image. The filtered color image and the denoised clear image are then fused to produce an enhanced, high-resolution HDR color image, and the disparity map and the mapped color image are updated based on the enhanced, high-resolution HDR color image.

Abstract: A camera device includes monochromatic and color image sensors that capture an image as a clear image in monochrome and as a Bayer image. The camera device implements image processing algorithms to produce an enhanced, high-resolution HDR color image. The Bayer image is demosaiced to generate an initial color image, and a disparity map is generated to establish correspondence between pixels of the initial color image and clear image. A mapped color image is generated to map the initial color image onto the clear image. A denoised clear image is applied as a guide image of a guided filter that filters the mapped color image to generate a filtered color image. The filtered color image and the denoised clear image are then fused to produce an enhanced, high-resolution HDR color image, and the disparity map and the mapped color image are updated based on the enhanced, high-resolution HDR color image.

Abstract: An amplifier architecture using actively phase-matched feed-forward linearization includes: a first signal path having a scaling amplifier 40 in series with a main amplifier 42; a second signal path having a replica amplifier 44 in series with a correction amplifier 46; and a combining node 48 that combines the first signal path and the second signal path. This topology places the scaling amplifier 40 in the main signal path. By inverting the scaling factor from &bgr; to 1/&bgr;, this topology retains the distortion cancellation property while balancing the two signal paths. In this case the scaling amplifier 40 attenuates the input signal rather than amplifying it. The end result remains the same. The main amplifier output signal is lower than the replica amplifier's by a factor of &bgr;. This results in a third-order distortion component that is &bgr;3 times bigger at the replica amplifier output.

Abstract: An amplifier architecture using actively phase-matched feed-forward linearization includes: a first signal path having a scaling amplifier 40 in series with a main amplifier 42; a second signal path having a replica amplifier 44 in series with a correction amplifier 46; and a combining node 48 that combines the first signal path and the second signal path. This topology places the scaling amplifier 40 in the main signal path. By inverting the scaling factor from &bgr; to 1/&bgr;, this topology retains the distortion cancellation property while balancing the two signal paths. In this case the scaling amplifier 40 attenuates the input signal rather than amplifying it. The end result remains the same. The main amplifier output signal is lower than the replica amplifier's by a factor of &bgr;. This results in a third-order distortion component that is &bgr;3 times bigger at the replica amplifier output.

Abstract: A data acquisition system uses an analog-to-digital converter (ADC) that includes a prediction feedback element. Using the computing power of a digital signal processor, the system predicts the next sample of the target signal based on pre-defined rules and previous samples. This digital prediction is converted to an analog signal using a digital-to-analog converter (DAC). An analog error summer compares the predicted signal with the target signal and creates an error signal. The digital signal processor uses the prediction error to more accurately predict the next sample. A negative feedback loop is thus formed by this system to drive the prediction error toward zero. Operating on the relatively small error signal in the forward and feedback paths enhances the conversion performance and data transfer efficiency.

Abstract: A data acquisition system uses an analog-to-digital converter (ADC) that includes a prediction feedback element. Using the computing power of a digital signal processor, the system predicts the next sample of the target signal based on pre-defined rules and previous samples. This digital prediction is converted to an analog signal using a digital-to-analog converter (DAC). An analog error summer compares the predicted signal with the target signal and creates an error signal. The digital signal processor uses the prediction error to more accurately predict the next sample. A negative feedback loop is thus formed by this system to drive the prediction error toward zero. Operating on the relatively small error signal in the forward and feedback paths enhances the conversion performance and data transfer efficiency.