Abstract: A novel process is taught for forming diodes in a process which simultaneously forms MOS or CMOS devices. These diodes have relatively low breakdown voltage, making them suitable for ESD protection devices or as voltage reference diodes. In alternative embodiments, novel low breakdown voltage devices are fabricated in a similar fashion as MOS devices but with doping levels such that the inherent bipolar device has a low breakdown voltage characteristic. In alternative embodiments, novel vertical bipolar transistors are taught, as are SCR devices, having low breakdown voltage characteristics. In one embodiment of this invention, a low breakdown voltage device is integrated directly with a standard MOS transistor, allowing the low breakdown voltage device to trigger the turn on of the standard MOS device, thereby providing large current capacity controlled by the low breakdown voltage device.

Abstract: A novel process is taught for forming diodes simulataneouly with the formation of typical prior art Ldd MOS devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.

Abstract: A novel process is taught for forming diodes simultaneously with the formation of typical prior art LDD MOS devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.

Abstract: A method of fabricating a self-aligned zener diode provides for N.sup.+ and P.sup.+ regions having the large dopant concentrations necessary for compatibility with shallow junction silicon gate CMOS devices. A contact region is provided on the substrate, doped with N-type dopant ions, and etched to cover a portion of the region in which a zener diode is to be formed. A P.sup.+ region is implanted using the doped contact region as a mask. Then, N-type dopant ions are diffused from the contact region to the underlying substrate, thereby providing self-aligned P.sup.+ and N.sup.+ regions having a well defined P-N junction.

Abstract: An integrated capacitor having an oxide layer of less than 500 .ANG. as a dielectric or insulator. A method of fabricating a capacitor including the steps of forming an oxide layer on a substrate, forming through the oxide layer a first capacitor plate in the substrate, and forming a second capacitor plate on the oxide layer. The method also includes the step of restructuring the oxide layer after the step of forming the first capacitor plate. Since the first capacitor plate is formed through the oxide layer the oxide layer can be grown on an undoped or lightly doped substrate; thus, the effects of the doping level on the growth rate of the oxide layer are eliminated and oxide layers having a uniform thickness of less than 500 .ANG. can consistently be provided.

Abstract: Capacitors or dual layer metalization interconnects are formed in an integrated circuit utilizing two layers of polycrystalline silicon (22, 24) separated by a thin insulation region (23). The insulation region formed between the two polycrystalline silicon regions has substantially fewer defects than the insulation regions used in prior art techniques due to the use of a unique process wherein the polycrystalline silicon layer (24) overlying the insulation layer (23) protects the insulation layer from attack during subsequent processing. An improved dielectric strength is provided by forming the insulation region (23) utilizing composite layers of silicon oxide (23a, 23c) and silicon nitride (23b).

Abstract: This invention significantly reduces the problem of undesired lateral diffusion of P type dopants into the P type active area. A thin oxide/nitride sandwich is formed on the surface of a semiconductor wafer and patterned to serve as a mask defining the to-be-formed active areas. An N type dopant implant is performed on the surface of the wafer to establish the desired field inversion threshold voltage. The wafer is then oxidized, with the oxide/nitride sandwich preventing oxide growth in the active areas. A layer of photoresist is applied to the wafer and patterned to expose the to-be-formed P well. That portion of the oxide exposed by the photoresist is removed, as is that portion of the substrate within the to-be-formed P well which contains N type dopants. P type impurities are then applied to the wafer. The photoresist is then removed and the P type dopants are diffused with little oxide growth to provide a P well having the desired dopant profile.