Abstract: An arrangement for generating a transmission clock signal and a reception clock signal is proposed in which only a single voltage-controlled oscillator is used, the reception clock signal being generated by phase-adjusting means whereas the transmission clock signal is generated directly by the voltage-controlled oscillator. Cross-talk between a plurality of voltage-controlled oscillators can be prevented in this way. Also, various measures are proposed for optimizing a circuit of this kind.

Abstract: A multiplexer cell (1) for converting an input signal (D0, D1) with a data input rate (fD) into an output signal (E) with a data output rate (fE), which in particular is twice the size of the data input rate, is proposed.

Abstract: A device and method is described for the frequency division of an input clock signal, in which from the input clock signal at least two output clock signals are generated, with an output pulse frequency equal to an input pulse frequency divided by a given factor, whereby with a phase detector a phase difference is measured between the at least two output signals and each of the at least two output clock signals is either inverted or not inverted, as a function of the phase difference determined. A method of this type is particularly suitable for the demultiplexing of an input data signal, and can also be designed to be multi-step.

Abstract: A method and an apparatus for scanning a data signal are provided whereby a plurality of scanning signals (P0, P1, P2, P3) delayed successively by a respective phase difference are generated, for example, by a quadrature oscillator (1). A first data signal (D) is scanned with these scanning signals (P0–P3) in order to generate a plurality of second data signals (D0–D3). Because the direction of rotation of the quadrature oscillator (1) can vary, depending on random starting conditions, the direction of rotation is determined by means of phase detectors (4). These phase detectors (4) are preferably connected to the outputs of the clock dividers (3). Depending on the direction of rotation determined, the second data signals (D0–D3) are allocated to output channels (A0–A3) by a change-over unit (6).

Abstract: Data reception circuit for receiving a serial input data stream, where the data reception circuit has a data stream separation circuit (4) for separating the serial input data stream into a plurality of separate data streams, a reference clock signal generation circuit (13) for generating a reference clock signal, a delay circuit (12) having a delay element chain (27) which comprises a plurality of series-connected delay elements, the first delay element (27-1) in the delay element chain (27) receiving the generated reference clock signal, and each delay element outputting a delayed reference clock signal (11), a first, asynchronously clocked register array (8), each register bank (26) in the first register array (8) being asynchronously clocked by an associated separate data stream and reading in the delayed reference clock signals from the delay circuit (12) in order to buffer-store a signal change in the separate data stream, a second, synchronously clocked register array (17), each register bank (28) in t

Abstract: A multiplexer cell (1) for converting an input signal (D0, D1) with a data input rate (fD) into an output signal (E) with a data output rate (fE), which in particular is twice the size of the data input rate, is proposed.

Abstract: Data reception circuit for receiving a serial input data stream with a high data transfer rate, where the data reception circuit has a data stream separation circuit (4) for separating the serial input data stream into a plurality of separate data streams with a reduced data transfer rate, a reference clock signal generation circuit (13) for generating a reference clock signal whose clock frequency corresponds to the data transfer rate of the separate data streams, a delay circuit (12) having a delay element chain (27) which comprises a plurality of series-connected delay elements, the first delay element (27-1) in the delay element chain (27) receiving the generated reference clock signal, and each delay element outputting a delayed reference clock signal via a signal output (11) in the delay circuit (12), a first, asynchronously clocked register array (8) which comprises a plurality of register banks (26), each register bank (26) in the first register array (8) being asynchronously clocked by an associated