Abstract: A transmission line. The transmission line includes a reference electrode. The transmission line also includes a stripline. The stripline meanders within a plane. The stripline has a non-planar profile when viewed along a direction parallel to the plane.

Abstract: One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.

Abstract: A transmission line includes a signal conductor and one or more return conductors, one or more of which having a stepped multi-layer structure. The return conductors may be disposed at opposite sides of the signal conductor. The return conductors may be multi-layer structures. At least some layers of each return conductor may have a stepped arrangement that defines a curve, such as an exponential curve. Additionally or alternatively, the signal conductor may be a stepped multi-layer structure, where at least some layers of the signal conductor may define a curve, such as an exponential curve. The signal conductor may be disposed at one or more upper layers of the transmission line or may be embedded at one or more layers near the center of the transmission line.

Abstract: An RF package assembly includes a stacked package-on-package arrangement of a first substrate and a second substrate. Each of the first and second substrates include RF signal pads and ground pads. An interface region between the stacked substrates couples the RF signal pads and ground pads of the first substrate to corresponding pads of the second substrate. The interface region includes galvanic connection regions providing a galvanic connection between the each of the first substrate ground pads and each of the corresponding second substrate ground pads. The interface region includes dielectric regions between each of the first substrate RF signal pads and the corresponding second substrate RF signal pads so that RF signals transmitted between the two substrates are capacitively coupled.

Abstract: A transmission line includes a signal conductor and one or more return conductors, one or more of which having a stepped multi-layer structure. The return conductors may be disposed at opposite sides of the signal conductor. The return conductors may be multi-layer structures. At least some layers of each return conductor may have a stepped arrangement that defines a curve, such as an exponential curve. Additionally or alternatively, the signal conductor may be a stepped multi-layer structure, where at least some layers of the signal conductor may define a curve, such as an exponential curve. The signal conductor may be disposed at one or more upper layers of the transmission line or may be embedded at one or more layers near the center of the transmission line.

Abstract: A flip chip device includes a substrate, an integrated circuit device, a mold compound, and a via. The substrate has a top side and a bottom side. The integrated circuit device is affixed to the bottom side of the substrate. The mold compound is affixed to the bottom side of the substrate. The via is affixed to the bottom side of the substrate. The via passes through the mold compound and is exposed at a bottom side of the mold compound. The via is coupled to a terminal of the integrated circuit device.

Abstract: A Radio Frequency, “RF”, component and a method of making the same. The component comprises a first electrically conductive signal member for conveying an RF signal and a second electrically conductive signal member for conveying an RF signal. The component also comprises a barrier located between the first signal member and the second signal member electromagnetically to shield the first and second signal members from each other. The barrier comprises a first row of electrically conductive shielding members spaced apart along a longitudinal axis of the first row, and a second row of electrically conductive shielding members spaced apart along a longitudinal axis of the second row. Each shielding member comprises a polyhedron. The shielding members of the first row are offset with respect to the shielding members of the second row to prevent a direct line of sight between the first signal member and the second signal member.

Abstract: A transmission line. The transmission line includes a reference electrode. The transmission line also includes a stripline. The stripline meanders within a plane. The stripline has a non-planar profile when viewed along a direction parallel to the plane.

Abstract: A semiconductor device may include an antenna array and a grounding assembly configured to at least partially electrically shield the antenna array. The grounding assembly may include a first grounding layer comprising a first plurality of openings and a second grounding layer comprising a second plurality of openings. The second grounding layer may at least partially occlude the first plurality of openings of the first grounding layer when viewed from above the antenna array.

Abstract: A method of testing a semiconductor device having a DC line configured to carry either a DC signal or a DC voltage and a circuit electrically connected to the DC line includes: during a first part of a test sequence, enabling a switch device so as to electrically connect a capacitor to the DC line via the switch device and applying a test signal to the circuit while the capacitor is electrically connected to the DC line; and during a second part of the test sequence, disabling the switch device so as to electrically disconnect the capacitor from the DC line via the switch device, injecting an AC signal onto the DC line after the capacitor is electrically disconnected from the DC line, and measuring a response of the circuit to the AC signal.

Abstract: A system may include a first power detector to measure a power level of a signal on a first transmitter channel, a second power detector to measure a power level of a signal on a second transmitter channel. The system may include a combiner to provide a combined signal associated with the signal on the first transmitter channel and the signal on the second transmitter channel, and a third power detector to measure a power level of the combined signal. The system may include a processing circuit to determine a relative phase difference between the signal on the first transmitter channel and the signal on the second transmitter channel based on results of measuring the power level of the signal on the first transmitter channel, measuring the power level of the signal on the second transmitter channel, and measuring the power level of the combined signal.

Abstract: An apparatus for determining whether an output signal from an injection locked oscillator is synchronized with an injection signal coming from an input oscillator has a distorter and a level detector. The distorter uses the output signal from the injection locked oscillator to generate a distorter output signal which has a difference tone in a predetermined frequency band if the output signal from the injection locked oscillator is not synchronized with the injection signal. The level detector is designed to detect a level of the difference tone. The apparatus determines, on the basis of the level of the difference tone, whether the output signal from the injection locked oscillator is synchronized with the injection signal.

Abstract: A method of testing a semiconductor device having a DC line configured to carry either a DC signal or a DC voltage and a circuit electrically connected to the DC line includes: during a first part of a test sequence, enabling a switch device so as to electrically connect a capacitor to the DC line via the switch device and applying a test signal to the circuit while the capacitor is electrically connected to the DC line; and during a second part of the test sequence, disabling the switch device so as to electrically disconnect the capacitor from the DC line via the switch device, injecting an AC signal onto the DC line after the capacitor is electrically disconnected from the DC line, and measuring a response of the circuit to the AC signal.

Abstract: An apparatus for determining whether an output signal from an injection locked oscillator is synchronized with an injection signal coming from an input oscillator has a distorter and a level detector. The distorter uses the output signal from the injection locked oscillator to generate a distorter output signal which has a difference tone in a predetermined frequency band if the output signal from the injection locked oscillator is not synchronized with the injection signal. The level detector is designed to detect a level of the difference tone. The apparatus determines, on the basis of the level of the difference tone, whether the output signal from the injection locked oscillator is synchronized with the injection signal.

Abstract: An integrated circuit is described herein. In accordance with one embodiment, the circuit includes a voltage controlled oscillator (VCO) that is configured to receive a tuning voltage at a tuning input and to provide an RF oscillator signal at an oscillator output. The circuit further includes a first and a second switchable resistor network. The first switchable resistor network includes at least a first resistor and at least a first switch and is connected between the tuning input of the VCO and a first node, which operably provides a first voltage. The second switchable resistor network includes at least a second resistor and at least a second switch and is connected between the tuning input of the VCO and a second node, which operably provides a second voltage.

Abstract: An integrated circuit is described herein. In accordance with one embodiment, the circuit includes a voltage controlled oscillator (VCO) that is configured to receive a tuning voltage at a tuning input and to provide an RF oscillator signal at an oscillator output. The circuit further includes a first and a second switchable resistor network. The first switchable resistor network includes at least a first resistor and at least a first switch and is connected between the tuning input of the VCO and a first node, which operably provides a first voltage. The second switchable resistor network includes at least a second resistor and at least a second switch and is connected between the tuning input of the VCO and a second node, which operably provides a second voltage.